EMIF Module Architecture
801
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
External Memory Interface (EMIF)
21.2.5.3 SDRAM Configuration Registers
The operation of the EMIF's SDRAM interface is controlled by programming the appropriate configuration
registers. This section describes the purpose and function of each configuration register, but
should be referred for a more detailed description of each register, including the default registers values
and bit-field positions. The following tables list the four such configuration registers, along with a
description of each of their programmable fields.
NOTE:
Writing to any of the fields: NM, CL, IBANK, and PAGESIZE in the SDRAM configuration
register (SDCR) causes the EMIF to abandon whatever it is currently doing and trigger the
SDRAM initialization procedure described in
Table 21-7. Description of the SDRAM Configuration Register (SDCR)
Parameter
Description
SR
This bit controls entering and exiting of the Self-Refresh mode. The field should be written using a byte-
write to the upper byte of SDCR to avoid triggering the SDRAM initialization sequence.
PD
This bit controls entering and exiting of the Power down mode. The field should be written using a byte-
write to the upper byte of SDCR to avoid triggering the SDRAM initialization sequence. If both SR and
PD bits are set, the EMIF will go into Self Refresh.
PDWR
Perform refreshes during Power Down. Writing a 1 to this bit will cause the EMIF to exit the power down
state and issue an AUTO REFRESH command every time Refresh May level is set. The field should be
written using a byte-write to the upper byte of SDCR to avoid triggering the SDRAM initialization
sequence. This bit should be set along with PD when entering power-down mode.
NM
Narrow Mode.
This bit defines the width of the data bus between the EMIF and the attached SDRAM
device. When set to 1, the data bus is set to 16-bits. When set to 0, the data bus is set to 32-bits. This
bit must always be set to 1.
CL
CAS latency.
This field defines the number of clock cycles between when an SDRAM issues a READ
command and when the first piece of data appears on the bus. The value in this field is sent to the
attached SDRAM device via the LOAD MODE REGISTER command during the SDRAM initialization
procedure as described in
. Only, values of 2h (CAS latency = 2) and 3h (CAS latency =
3) are supported and should be written to this field. A 1 must be simultaneously written to the
BIT11_9LOCK bit field of SDCR in order to write to the CL bit field.
IBANK
Number of Internal SDRAM Banks.
This field defines the number of banks inside the attached SDRAM
devices in the following way:
• When IBANK = 0, 1 internal bank is used
• When IBANK = 1h, 2 internal banks are used
• When IBANK = 2h, 4 internal banks are used
This field value affects the mapping of logical addresses to SDRAM row, column, and bank addresses.
See
for details.
PAGESIZE
Page Size.
This field defines the internal page size of the attached SDRAM devices in the following way:
• When PAGESIZE = 0, 256-word pages are used
• When PAGESIZE = 1h, 512-word pages are used
• When PAGESIZE = 2h, 1024-word pages are used
• When PAGESIZE = 3h, 2048-word pages are used
This field value affects the mapping of logical addresses to SDRAM row, column, and bank addresses.
See
for details.
Table 21-8. Description of the SDRAM Refresh Control Register (SDRCR)
Parameter
Description
RR
Refresh Rate
. This field controls the rate at which attached SDRAM devices will be refreshed. The
following equation can be used to determine the required value of RR for an SDRAM device:
• RR = f
EMIF_CLK
/ (Required SDRAM Refresh Rate)
More information about the operation of the SDRAM refresh controller can be found in
