Module Operation
1225
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
FlexRay Module
26.2.1.1.2 Transfer Configuration RAM
The Transfer Configuration RAM (TCR) consists of 128 entries, one entry for each possible FlexRay
buffer. Entry 1 is assigned to FlexRay buffer 1, entry 2 to FlexRay buffer 2,..., and entry 128 is assigned to
FlexRay buffer 128.
Each TCR entry defines:
•
data transfer size ( data, header only or data only)
•
whether the transmit request flag (STRXH) should be set for the data transferred by the FTU to the CC
to send out the data to the FlexRay bus.
•
the 14-bit buffer address offset, which, in combination with the Transfer Base Address defined in TBA,
specifies the start of the corresponding FlexRay message buffer in the system memory RAM.
NOTE:
It is recommended to clear the whole TCR before configuring it, in order to avoid unexpected
transfer behavior due to old configuration contents or random TCR RAM contents after
power on reset.
If a transfer is triggered but no transfer size (header or data) is setup in the TCR, no data will
be transferred, but the corresponding flag in the Transfer to Communication Controller
Occurred (TCCOx) or the Transfer to System Memory Occurred (TSMOx) will be set.
26.2.1.1.2.1 ECC Protection
The Transfer Configuration RAM (TCR) is ECC protected. The ECC multi-bit error interrupt generation is
disabled by default and can be switched on by writing a 4 bit key to dedicated ECC lock bits in the Global
Control Set/Reset Register (GCS/R).
The ECC protection supports single-bit error correction and double-bit error detection mechanism
(SECDED). The ECC information is stored together with the corresponding 19-bit data word entry.
The ECC is checked each time a data word is read from the TCR RAM. If an ECC error is detected, the
PE error flag is set in the Transfer Error Interrupt Flag (TEIF) register. The detection of an ECC single-bit
error will be indicated by the SE flag in the TCR Single-Bit Error Status (TSBESTAT).
Additionally an uncorrectable RAM error interrupt/event will be generated. The uncorrectable RAM error
interrupt/event is non maskable and therefore cannot be switched off. For ECC single-bit errors, the
uncorrectable RAM error interrupt/event is generated, if the ECC single-bit error correction is disabled.
The uncorrectable RAM error is hooked up to the ESM module (event).
The faulty TCR RAM address can be read from the ECC Error Address (PEADR) register. Equivalent
information is available for ECC single-bit errors in the TCR Single-Bit Error Status (TSBESTAT) register.
Independent of the ECC single-bit error correction being enabled or disabled, the TSBESTAT is updated.
See
for more details.
26.2.1.1.3 Memory Protection Mechanism
This feature allows to restrict accesses to certain areas in memory in order to protect critical application
data from unintentionally being accessed by the Transfer Unit State Machine.
One memory section (start and end address) can be defined, which allows read and write accesses for the
Transfer Unit State Machine.
If the end address is smaller or equal to the start address, data transfers will be blocked. Any accesses
performed outside this memory area by the Transfer Unit State Machine result in no transfers being
performed. In case of a protection violation a flag will be set and the Memory Protection Violation interrupt
will be activated. The Transfer Unit State Machine will be disabled in this case.
The default setting of the Transfer Unit State Machine memory protection address range setup is
0x00000000 for start address and 0x00000000 for end address.
This means a valid address range must be setup, before the Transfer Unit can be used.
