CPU Interconnect Subsystem
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SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Interconnect
4.3.4 Interconnect Self-test
CPU Interconnect Subsystem can be put into self-test. When in self-test, the self-test logic will apply test
stimulus to each master and slave interface. If an error is detected, the type of error for the corresponding
interface is logged. An error is asserted to ESM Group 3 if the self-test does not complete successfully.
NOTE:
Application must only launch CPU Interconnect Subsystem self-test when there are no bus
transactions from any masters including the CPU cores. While in self-test, the interconnect
can not service any requests. Bus master requests can be lost or corrupted. It is recommend
that the self-test is only exercised as part of the device initialization before any master is
setup by the CPU.
To launch the self-test, the applicable must follow the below sequence:
1. Write 0xA key to the DTC_ERROR_RESET bits of the SCMCNTRL register in the SCM module.
2. CPU executes WFI instruction to put itself in idle state. The start of self-test is gated by the idle state of
the CPU.
3. When both step 1 and 2 are met, the self-test will start. While self-test is on-going, the CPU cores is
forced into reset. Note that reset is only held to the CPU cores while the rest of the system is not.
4. When self-test is complete, the DTC_ERROR_RESET bits is automatically reverted back to 0x5 as the
reset value.
5. After the self-test is complete, a reset is applied to the CPU Interconnect Subsystem for 16 HCLK
cycles. During this time, the CPU is also held in reset.
6. After the interconnect and the CPU comes out of the reset, normal code execution can then start. CPU
can check the self-test status by reading the NT_OK bit and the PT_OK bit of the SDC_STATUS
register. These two bits indicate if the negative test and positive self-test sequence have passed. In
addition, if the self-test has failed, the error is asserted to the ESM module.
4.3.5 Interconnect Timeout
The CPU Interconnect Subsystem contains timeout counters to count the amount of time it is taking for a
master request to be accepted by the slave and also to count the amount of time it takes from an
accepted request to the slave response. There are two separate counters per master interface. When
either the request-to-accept counter or the accept-to-response counter expires by the slave, a timeout
error is asserted to the ESM. The counter threshold value beyond which the timeout error will be
generated is programmable in the SCM module. When a timeout happens to an interface, the request-to-
accept timeout error is captured in the SCM's SCMIAERR0STAT register and the accept-to-response
timeout error is captured in the SCMIAERR1STAT. See
for the mapping between each interface
to each bit field. Application needs to write 0xA key to the TO_CLEAR bits of the SCMCNTRL register to
reset the timeout logic inside the CPU Interconnect Subsystem as part of the error handling in the ISR.
