Module Operation
391
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Level 2 RAM (L2RAMW) Module
8.2.2.5
Support for Cortex-R5F CPU's Address and Control Bus Parity Checking
The Cortex-R5F CPU provides parity bits for the address and control signals going to L2RAMW. The
L2RAMW module also computes the parity bits based on the CPU's address bus and control signals. The
computed parity bits are compared against the parity bits received from the CPU. A mismatch is recorded
as Address/Control parity error (bit 8) in the RAMERRSTATUS register and signaled as an Address Parity
Failure to the Error Signaling Module (ESM). It also generates a bus error.
The error flag in the RAMERRSTATUS register must be cleared by the application in order for the
L2RAMW interface module to continue capturing subsequent errors and error addresses.
NOTE:
No Change Of Parity Scheme On-The-Fly:
The L2RAMW interface module does not
support on-the-fly change to the parity scheme being used for checking the CPU address
bus and control bus. The application must ensure that the parity polarity (odd or even) is not
changed while there is an ongoing access to the L2RAM.
8.2.2.6
Redundant Address Decode
The L2RAMW module generates the memory selects for each of the L2RAMW banks as well as the ECC
memory based on the CPU address. The logic to generate these memory selects is duplicated and the
outputs compared to detect any address decode errors. A mismatch is indicated as an Address Error to
the Error Signaling Module (ESM). The L2RAMW or ECC address that caused the fault is captured in the
RAMUERRADDR register. This is a 64-bit address that is stored as an offset from the base of the
L2RAMW or ECC memory.
As described earlier, each individual physical RAM bank is 36 bits wide. Each RAM bank contributes 32
bits of data and 4 bits of ECC when the bus master performs a 64-bit read from the L2RAM. Each
L2RAMW bank receives a memory select and the address from the L2RAMW interface module. Any
difference between the address and the memory selects results in wrong data and ECC pair being sent to
the CPU. The CPU's SECDED block will detect this data error.
The L2RAMW interface module also supports a mechanism to test the operation of the redundant address
decode logic and the compare logic. This testing is supported by providing a test stimulus, and can be
triggered by the application by configuring the RAMTEST register. The address of any error identified
during testing of the redundant address decode and compare logic is not captured in the
RAMUERRADDR register.
NOTE:
Address decode checking when in compare logic test mode:
When the address decode
and compare logic test mode is enabled, the redundant address decode and compare logic
is not available for checking the proper generation of the memory selects for the L2RAMW
and ECC memory.
