Overview
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SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Error Profiling Controller (EPC)
12.1 Overview
The EPC is used as a diagnostic for functional safety purposes.
The primary goal of this module is to provide a unified correctable ECC error (single-bit ECC fault) profiling
capability and error address cache on ECC failures in system bus memory slaves like Flash, FEE, and
SRAM.
The secondary goal of this module is to provide an ECC error reporting capability for bus masters which
are not natively built to manage ECC error like the interconnect.
The EPC can not distinguish between memory failure and interconnect failure. A fault address may not
always mean there is a true issue in the memory. EPC captures both the correctable and uncorrectable
information.
The EPC supports the following features:
•
Traps the correctable and uncorrectable faults from RAM, CPU, and Interconnect.
•
For correctable fault, EPC will keep track of unique addresses through the usage of Content Address
Memory (CAM).
•
Allow CPU accessing CAM to set or clear any CAM entry index and/or content during execution run
time as well as diagnosing the CAM.
•
Trigger error event to Error Signaling Module (ESM) and keep track of error in status register for user
query.
12.2 Module Operation
shows the typical usage of EPC in device architecture. In the EPC chapter, the CPU, RAM, or
Interconnect is referred to as IP. The Error Profiling Module section in the Architecture chapter indicates
which IP correctable and uncorrectable event are hooked up to EPC. Each IP can provide either or both
correctable and uncorrectable fault event to EPC. The EPC chapter will mention IP correctable or
uncorrectable fault event with generic description of how EPC process these fault events.
EPC captures the uncorrectable address from IP that are not natively built to manage ECC error like
interconnect and triggers uerr_event to ESM. See
for more details.
EPC performs error profiling on the correctable fault and trigger serr_event to ESM if the address of the
correctable fault is not part of the CAM and SERRENA control bits are set to enable values. Detail
description of error profiling definition is described in
. Each single fault correctable IP has a
FIFO to buffer correctable fault address input. Following is the behavior of FIFO and CAM operation:
1. If FIFO overflow happens on a particular ECC correctable IP, EPC will set the corresponding FIFO
Overflow Bit in the Overflow Status Register (OVRFLWSTAT) and trigger serr_event.
2. If any of the FIFOs is full (any FIFOFULLSTAT(x) is set), EPC will trigger the cam_fifo_full_int port if
CAM/FIFO full interrupt enable (EPCCNTRL(24)) is set.
3. If CAM indexes are all occupied, EPC will set the CAM Full Bit in EPCERRSTAT register and trigger
the cam_fifo_full_int port if CAM/FIFO full interrupt enable is set.
4. If CAM overflow happens, EPC will set CAM overflow status bit (cam ovflw) in EPCERRSTAT register.
5. You can access CAM content and CAM index during functional and diagnostic run time.
