Instruction Set
1075
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
High-End Timer (N2HET) Module
Execution
/ Notes: IR1, IR2 are 32-bit intermediate results
// SRC1, SRC2 are 32-bit sources selected
//
by fields src1, src2
// IC1, IC2 are intermediate values of the carry flag
// IZ1, IZ2 are intermediate values of the zero flag
// IN1, IN2 are intermediate values of the negative flag
// IV1, IV2 are intermediate values of the overflow flag
// scount is the shift count (0 to 31) specified by C12:C8
/********** SOURCE OPERAND DECODING STAGE **********/
switch (C22:C19)
{
case 0000:SRC1[31:0] = 0x00000000
case 0001:SRC1[31:0] = Immediate Data Field D[31:0]
case 0010:SRC1[31:8] = A[24:0]; SRC1[6:0] = 0
case 0011:SRC1[31:8] = B[24:0]; SRC1[6:0] = 0
case 0100:SRC1[31:0] = R[31:0]
case 0101:SRC1[31:0] = S[31:0]
case 0110:SRC1[31:0] = T[31:0]
case 0111:SRC1[31:0] = 0xFFFFFFFF
case 1000:SRC1[31:0] = Remote Data Field D[31:0]
case 1001:SRC1[31:9] = 0; SRC1[8:0] = Remote Program Field P[8:0]
}
switch (C18:C16)
{
case 000:SRC2[31:0] = 0x00000000
case 001:SRC2[31:0] = Immediate Data Field[31:0]
case 010:SRC2[31:8] = A[24:0]; SRC2[6:0] = 0
case 011:SRC2[31:8] = B[24:0]; SRC2[6:0] = 0
case 100:SRC2[31:0] = R[31:0]
case 101:SRC2[31:0] = S[31:0]
case 110:SRC2[31:0] = T[31:0]
case 111:SRC2[31:0] = 0xFFFFFFFF
}
/******** ARITHMETIC / LOGICAL OPERATION STAGE *******/
switch (C[25:23])
{
case 011:IR1 = src1 + src2 + C // ADC
case 001:IR1 = src1 + src2 // ADD
case 010:IR1 = src1 & src2 // AND
case 100:IR1 = src1 | src2 // OR
case 110:IR1 = src1 - src2 - C // SBB
case 101:IR1 = src1 - src2 // SUB
case 111:IR1 = src1 ^ src2 // XOR
}
IC1 = Carry Out if Operation is ADD, ADC, SUB, SBB
= 0 if Operation is AND, OR, XOR
IZ1 = Set if IR1 is zero, Clear if IR1 is non-zero
IN1 = IR[31]
IV1 = (IC1 XOR IR1[31]) AND NOT(SRC1[31] XOR SRC2[31])
/******************** SHIFT STAGE ********************/
switch (C15:C13)
{
case 000: // smode = No Shift
IR2 = IR1
IC2 = IC1; IZ2 = IZ1; IN2 = IN1; IV2 = IV1;
case 001: // smode = Arithmetic Shift Right
IR2[31 - scount : 0] = IR1[31:scount]
if (scount>0) {
IR2[31 : 31 - 1] = IR1[31]
