Frame
Offset Value
Base + 0x00
0x20
Initial Source Address
Channel Configuration
Initial Destination Address
Element
Offset Value
Initial Transfer Count
Frame
Offset Value
Initial Source Address
Channel Configuration
Current Source Address
Initial Destination Address
Element
Offset Value
Current Destination Address
Initial Transfer Count
Frame
Offset Value
Current Transfer Count
0x30
0x800
Current Source Address
Current Source Address
Reserved
Reserved
Reserved
Current Destination Address
Current Destination Address
Current Transfer Count
Current Transfer Count
0x1F0
0x1E0
0x810
0x8F0
Base + 0xXXXC
Reserved
0x10
Primary CP0
Primary CP1
Primary CPnn
Working CP0
Working CP1
Working CPnn
Base + 0XXX0
Base + 0xXXX4
Base + 0xXXX8
Initial Source Address
Channel Configuration
Initial Destination Address
Initial Transfer Count
Element Offset Value
}
}
}
}
}
}
Y
...
DMAREQ(0)
DMAREQ(1)
DMAREQ(2)
DMAREQ(63)
Ch 0
Control Packet 0
Y
...
CH1ASI[5:0]
DMAREQ(0)
DMAREQ(1)
DMAREQ(2)
DMAREQ(63)
CH0ASI[5:0]
Control Packet 1
YY
.
Control Packet 31
Ch 1
Y
...
CH31ASI[5:0]
DMAREQ(0)
DMAREQ(1)
DMAREQ(2)
DMAREQ(63)
Ch 31
Y
...
Module Operation
702
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Direct Memory Access Controller (DMA) Module
Figure 20-4. DMA Request Mapping and Control Packet Organization
Figure 20-5. Control Packet Organization and Memory Map
