8, 16, or 32 bit
WR_DATA[xx:0]
Module Operation
2159
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
RAM Trace Port (RTP)
Example: For a 16-bit port and with data of 16-bit, the last transfer has to be padded with eight 0s. This
effectively results in a transfer of 48 bits instead of 40. However the whole transfer is completed in 3
RTPCLK cycles.
For a detailed description of the representation of the packet on the RTP port pins, refer to
37.2.2 Direct Data Mode (DDM)
In this mode, data is written directly by the CPU or other master to a dedicated capture register
(RTPDDMW). The data is then transferred from the capture register to the FIFO. In a different
configuration the module traces the data on read operations on the RAM directly into the FIFOs. In Direct
Data Mode, no information other than the actual data is transmitted. The address of the written data can
only be determined by the order of writes or reads by the CPU or other master. This mode is especially
useful if a block of data on consecutive addresses has to be transmitted.
The transfer size (8, 16, or 32 bit) is programmable, but cannot be dynamically changed. Data not
written/read in the correct transfer size will be truncated/extended. For example, if the transfer size is
programmed to 16 bits and a 32-bit write operation is performed, the data written to the FIFO will be 32-bit
wide, however only the upper 16 bits of the FIFO will be transmitted. If an 8-bit operation is performed, bits
8-15 of the FIFO will be indeterminate, so the upper 8 bits of the data transmitted are dependent on the
previous contents of the FIFO RAM.
When the module is configured in Direct Data Mode (TM_DDM = 1) to trace write operations (DDM_RW =
1) to the RTPDDMW register, the programming of the trace regions for all FIFOs will be ignored and data
tracing, when accessing the addresses defined by the regions, will not occur. If the module is configured in
read mode (DDM_RW = 0), and if the read access to a RAM block falls into a valid trace region, the data
will be traced into the corresponding FIFO for this RAM block. Since no address information is transmitted
in Direct Data Mode, the executing program has to make sure that one FIFO is completely empty
(RTPGSR register), before new data is traced into the next FIFO.
37.2.2.1 Packet Format in Direct Data Mode
In Direct Data Mode write or read operations, only the data written to the RTP direct data mode write
register (RTPDDMW) or the data read from RAM, and therefore captured into the FIFO, will be
transmitted. The packet length is programmable (8, 16, or 32 bits).
illustrates this format.
Figure 37-4. Packet Format in Direct Data Mode
37.2.3 Trace Regions
To limit the amount of data to be trace, two trace regions per RAM or peripheral are implemented. These
can be programmed to specific start addresses and block sizes. Depending on the device configuration
(number of RAM blocks), not all regions might be implemented. Trace regions are used in Trace Mode for
read or write trace and in Direct Data Mode for read trace. In Direct Data Mode write configuration, the
data has to be written directly to the RTP direct data mode write register (RTPDDMW).
The RAM and peripherals start at fixed addresses in the devices memory map. With this the start address
of a region does not need to be specified with its full 32-bit address. For RAM regions, only the lower 18-
bit need to be programmed. The peripheral address frame covers a wider range and the start address
needs to be programmed with the lower 24-bit.
The trace regions do not support a programmable end address; however, a block size needs to be
specified for each region. The block size can be chosen from as low as 256 Bytes up to 256 kBytes
(128 kBytes for peripherals).
