FlexRay Module Registers
1362
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
FlexRay Module
WAKEUP
Go to POC state WAKEUP when called in POC state READY. When called in any other state, CMD will
be reset to 0000 = command_not_accepted.
RUN
Go to POC state STARTUP when called in POC state READY. When called in any other state, CMD will
be reset to 0000 = command_not_accepted.
ALL_SLOTS
Leave single slot mode after successful startup / integration at the next end of cycle when called in POC
states NORMAL_ACTIVE or NORMAL_PASSIVE. When called in any other state, CMD will be reset to
0000 = command_not_accepted.
HALT
Set the Halt request HRQ bit in the communication controller status vector register and go to POC state
HALT at the next end of cycle when called in POC states NORMAL_ACTIVE or NORMAL_PASSIVE.
When called in any other state, CMD will be reset to 0000 = command_not_accepted.
FREEZE
Go to POC state HALT immediately and set the Freeze status Indicator FSI bit in the communication
controller status vector register. Can be called from any state.
SEND_MTS
Send single MTS symbol during the symbol window of the following cycle on the channel configured by
MTSA, MTSB, when called in POC state NORMAL_ACTIVE. When called in any other state, CMD will be
reset to 0000 = command_not_accepted.
ALLOW_COLDSTART
The command resets bit CSI in the CCSV register to enable coldstarting of the node when called in any
POC state except DEFAULT_CONFIG, CONFIG or HALT. When called in these states, CMD will be reset
to 0000 = command_not_accepted.
RESET_STATUS_INDICATORS
Reset status flags FSI, HRQ, CSNI, and CSAI in the communication controller status vector register.
CLEAR_RAMS
Sets bit CRAM in the message handler status register when called in DEFAULT_CONFIG or CONFIG
state. When called in any other state, CMD will be reset to 0000 = command_not_accepted. Bit CRAM is
also set when the communication controller leaves hardware reset. By setting bit CRAM, all internal RAM
blocks are initialized to 0 and the ECC bits are initialized accordingly, depending what mode is enabled.
During the initialization of the RAMs, PBSY will show POC busy. Access to the configuration and status
registers is possible during execution of CHI command CLEAR_RAMS.
The initialization of the Communication Controller internal RAM blocks takes 2048 VBUS clock cycles.
There should be no host access to IBF or OBF during initialization of the internal RAM blocks after
hardware reset or after assertion of controller host interface command CLEAR_RAMS. Before asserting
controller host interface command CLEAR_RAMS the host should be aware that no transfer between
message RAM and IBF / OBF or the transient buffer RAMs is ongoing. This command also resets the
message buffer status registers (MHDS, TXRQ1/2/3/4, NDAT1/2/3/4, MBSC1/2/3/4).
NOTE:
All accepted commands with exception of CLEAR_RAMS and SEND_MTS will cause a
change of the POC state in the VBUS clock domain after at most 8 cycles of the slower of
the two clocks VBUS clock and 80MHz sample clock coming from the PLL. It is assumed
that POC was not busy when the command was applied and that no POC state change was
forced by bus activity in that time frame. Reading register Communication Controller Status
Vector (CCSV) will show data that is additionally delayed by synchronization from sample
clock to VBUS clock domain and by the CPU interface. The maximum additional delay is 12
cycles of the slower of the two clocks VBUS clock and sample clock.
