Control Registers
1543
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Multi-Buffered Serial Peripheral Interface Module (MibSPI) with Parallel Pin
Option (MibSPIP)
Table 28-13. SPI Flag Register (SPIFLG) Field Descriptions (continued)
Bit
Field
Value
Description
3
DESYNCFLG
Desynchronization of slave device. Desynchronization monitor is active in master mode only.
This flag can be cleared by one of the following methods:
• Write a 1 to this bit.
• Clear the SPIEN bit to 0.
0
No slave desynchronization detected.
1
A slave device is desynchronized. The master monitors the ENAble signal coming from the
slave device and sets the DESYNC flag after the last bit is transmitted plus t
T2EDELAY
. If
DESYNCENA is set an interrupt is asserted. Desynchronization can occur if a slave device
misses a clock edge coming from the master.
2
PARERRFLG
Calculated parity differs from received parity bit. If the parity generator is enabled (can be
selected individually for each buffer) an even or odd parity bit is added at the end of a data
word. During reception of the data word the parity generator calculates the reference parity and
compares it to the received parity bit. In the event of a mismatch the PARITYERR flag is set
and an interrupt is asserted if PARERRENA is set. This flag can be cleared by one of the
following methods:
• Write a 1 to this bit.
• Clear the SPIEN bit to 0.
0
No parity error detected.
1
A parity error occurred.
1
TIMEOUTFLG
Time-out caused by nonactivation of ENA signal. This flag can be cleared by one of the
following methods:
• Write a 1 to this bit.
• Clear the SPIEN bit to 0.
0
No ENA-signal time-out occurred.
1
An ENA signal time-out occurred. The SPI generates a time-out because the slave has not
responded in time by activating the ENA signal after the chip select signal has been activated. If
a time-out condition is detected the corresponding chip select is deactivated immediately and
the TIMEOUT flag is set. In addition the TIMEOUT flag in the status field of the corresponding
buffer is set. The transmit request of the concerned buffer is cleared, that is, the SPI does not
re-start a data transfer from this buffer.
0
DLENERRFLG
Data-length error flag. This flag can be cleared by one of the following methods:
• Write a 1 to this bit.
• Clear the SPIEN bit to 0.
Note: Whenever any transmission errors (TIMEOUT, BITERR, DLEN_ERR, PARITY_ERR,
DESYNC) are detected and the error flags are cleared by writing to the error bit in the
SPIFLG register, the corresponding error flag in SPIBUF does not get cleared. Software
needs to read the SPIBUF until it becomes empty before proceeding. This ensures that
all of the old status bits in SPIBUF are cleared before starting the next transfer.
0
No data length error has occurred.
1
A data length error has occurred.
