SCI/LIN Control Registers
1678
SPNU563A – March 2018
Copyright © 2018, Texas Instruments Incorporated
Serial Communication Interface (SCI)/ Local Interconnect Network (LIN)
Module
29.7.5 SCI Clear Interrupt Register (SCICLEARINT)
and
illustrate this register. SCICLEARINT register is used to clear the enabled
interrupts without accessing SCISETINT register.
Figure 29-32. SCI Clear Interrupt Register (SCICLEARINT) (offset = 10h)
31
30
29
28
27
26
25
24
CLR BE INT
CLR PBE INT
CLR CE INT
CLR ISFE INT
CLR RE INT
CLR FE INT
CLR OE INT
CLR PE INT
R/WL-0
R/WL-0
R/WL-0
R/WL-0
R/WL-0
R/W-0
R/W-0
R/W-0
23
19
18
17
16
Reserved
CLR
RX DMA ALL
CLR
RX DMA
CLR
TX DMA
R-0
R/WC-0
R/W-0
R/W-0
15
14
13
12
10
9
8
Reserved
CLR ID INT
Reserved
CLR RX INT
CLR TX INT
R-0
R/WL-0
R-0
R/W-0
R/W-0
7
6
5
4
3
2
1
0
CLR
TOA3WUS INT
CLR
TOAWUS INT
Reserved
CLR
TIMEOUT INT
Reserved
CLR
WAKEUP INT
CLR
BRKDT INT
R/WL-0
R/WL-0
R-0
R/WL-0
R-0
R/W-0
R/WC-0
LEGEND: R/W = Read/Write; R = Read only; WL = Write in LIN mode only; WC = Write in SCI-compatible mode only; -
n
= value after reset
Table 29-17. SCI Clear Interrupt Register (SCICLEARINT) Field Descriptions
Bit
Field
Value
Description
31
CLR BE INT
Clear bit error interrupt. This bit is effective in LIN mode only. This bit disables the bit error
interrupt when set.
0
Read:
The interrupt is disabled.
Write:
No effect.
1
Read:
The interrupt is enabled.
Write:
The interrupt is disabled.
30
CLR PBE INT
Clear physical bus error interrupt. This bit is effective in LIN mode only. This bit disables the
physical-bus error interrupt when set.
0
Read:
The interrupt is disabled.
Write:
No effect.
1
Read:
The interrupt is enabled.
Write:
The interrupt is disabled.
29
CLR CE INT
Clear checksum-error interrupt. This bit is effective in LIN mode only. This bit disables the
checksum interrupt when set.
0
Read:
The interrupt is disabled.
Write:
No effect.
1
Read:
The interrupt is enabled.
Write:
The interrupt is disabled.
28
CLR ISFE INT
Clear inconsistent-synch-field-error (ISFE) interrupt. This bit is effective in LIN mode only. This
bit disables the ISFE interrupt when set.
0
Read:
The interrupt is disabled.
Write:
No effect.
1
Read:
The interrupt is enabled.
Write:
The interrupt is disabled.