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94
Operating Memory Area
Section 4-4
Output
Model
Words
Bits
Name
Operation
Reference
X
axis
Y
axis
Z
axis
U
axis
NC4
@
3
NC2
@
3
NC1
@
3
n
n
n
n+2
n+2
n+4
n+6
00
Memory
operation
commands
Sequence
Number
Enable
In memory operation, this setting specifies
whether the sequence number designated
in the operating data area is enabled or
disabled for beginning operation.
SECTION 8
Memory
Operation
01
START
At the rising edge (
↑
) when this bit turns
ON, memory operation starts.
02
INDEPEN-
DENT START
At the rising edge (
↑
) when this bit turns
ON, memory operation starts. The com-
pletion code is treated as “terminating,”
except for when it is set to “bank end.”
03
Direct opera-
tion com-
mands
ABSOLUTE
MOVEMENT
At the rising edge (
↑
) when this bit turns
ON, direct operation is started with the
position designated in the operating data
area treated as an absolute position.
SECTION 7
Direct Opera-
tion
04
RELATIVE
MOVEMENT
At the rising edge (
↑
) when this bit turns
ON, direct operation is started with the
position designated in the operating data
area treated as a relative position.
05
INTERRUPT
FEEDING
At the rising edge (
↑
) when this bit turns
ON, interrupt feeding begins for direct
operation.
9-3 Interrupt
Feeding
06
Origin posi-
tioning com-
mands
ORIGIN
SEARCH
At the rising edge (
↑
) when this bit turns
ON, an origin search is executed.
SECTION 6
Defining the
Origin
07
ORIGIN
RETURN
At the rising edge (
↑
) when this bit turns
ON, positioning returns to the origin.
08
PRESENT
POSITION
PRESET
At the rising edge (
↑
) when this bit turns
ON, the present position is forcibly
changed to the position set in the operat-
ing data area, and then the origin is estab-
lished based on the changed present
position.
NC4
@
3
NC2
@
3
NC1
@
3
n
n
n
n+2
n+2
n+4
n+6
09
Commands
for special
functions
JOG (speed
feeding)
When this bit turns ON, jogging (speed
feeding) is executed.
9-1 Jogging
10
Direction des-
ignation
This designates the direction for when
JOG or INTERRUPT FEEDING are exe-
cuted.
9-3 Interrupt
Feeding
11
TEACH
At the rising edge (
↑
) when this bit turns
ON, the teaching operation is executed.
9-2 Teaching
12
RELEASE
PROHIBIT/
ERROR
RESET
At the rising edge (
↑
) when this bit turns
ON, the error status is cleared and the
pulse output prohibition is released.
11-6 Releas-
ing Pulse
Output Prohi-
bition and
Resetting
After Errors
13
Error counter
reset output/
origin-adjust-
ment com-
mand output
When this bit turns ON, error counter reset
output/origin-adjustment command output
turns ON.
9-7 Error
Counter
Reset Output
and Origin
Adjustment
Command
Output
14
Override
enable
This bit enables or disables the override
function.
9-6 Override
15
STOP
At the rising edge (
↑
) when this bit turns
ON, positioning is decelerated to a stop.
9-5 Decelera-
tion Stop
NC4
@
3
NC2
@
3
NC1
@
3
n+1
n+1
n+1
n+3
n+3
n+5
n+7
00
to
07
Not used
---
---
08
FORCED
INTERRUPT
In memory operation, at the rising edge
(
↑
) when this bit turns ON, forced interrupt
is started.
9-4 Forced
Interrupt
09
to
11
Not used
---
---
Summary of Contents for CS1W-213 - REV 02-2008
Page 2: ...CS1W NC113 213 413 133 233 433 Position Control Units Operation Manual Revised February 2008 ...
Page 3: ...iv ...
Page 13: ...xiv ...
Page 15: ...xvi ...
Page 19: ...xx ...
Page 43: ...18 Basic Operational Flow Section 2 1 ...
Page 87: ...62 Servo Relay Unit Section 3 7 ...
Page 199: ...174 Z phase Margin Section 6 8 ...
Page 217: ...192 Sample Program Section 7 7 ...
Page 285: ...260 Easy Backup Function Ver 2 0 or later Section 9 11 ...
Page 377: ...352 Common Parameter Area Appendix C ...