GE Brivo OEC 715, Service Manual

Page: 111 / 551

System Overview
2-57
When filament focus switches, PWM pulses will shut down for a while delay of 56mS, because operate time
of relay is about 7mS and RC circuit of coil of relay costs about 6mS. The delay time should be more than
13mS. The delay signal is produced by CD4538 and logic gates. The delay time is determined by R42, C29
and R41, C28.
10V reference
The U7 REF102 chip provides st10V for regulating circuit.
Interlock
The J1A-13 and J1C-13 pin of connector are connected as interlock. The interlock goes through the FDB to
verify that the FDB is in place.
Interface
Name Description Pin Attribution Scale Comment
GND GND J1A-12, J1A-32, J1B-12, J1C-12, Ground GND GND
15V +15V J1A-29, J1B-29, J1C-29 Power 15V 15V
15NV -15V J1C-32 Power -15V -15V
24V +24V J1A-1, J1B-1, J1C-1 Power +24V +24V
24V_GND GND of 24V J1A-6, J1B-6, J1C-6 Ground GND GND of 24V
MAC_FDB Set current value J1B-9 Analog 0V~15V
PWMC_FDB Control voltage
output
J1B-13 Analog -15V~15V
FILDIS_FDB Filament disable J1C-10 Digital 0V/15V 15V=effective
FCSSW_FDB Large or small
filament switch
J1A-10 Digital 0V/15V 0V= small
15V=large
OCALM_FDB Over current alarm
signal output
J1B-10 Digital 0V/15V 15V=effective
FILLA2 Large filament J1A-18, J1B-18, J1C-18 Analog 0V~24V
FILLA1 Large filament J1A-20, J1B-20, J1C-20 Analog 0V~24V
FILSM1 Small filament J1A-22, J1B-22, J1C-22 Analog 0V~24V
FILSM2 Small filament J1A-24, J1B-24, J1C-24 Analog 0V~24V
FILCOM Filament common
port
J1A-26, J1B-26, J1C-26 Analog 0V~24V
Interlock_B Interlock_B J1A-13 Digital 0V/24V
Interlock_C Interlock_C J1C-13 Digital 0V/24V
Test point
Name Pin Description
FC TP1 Return current
PWMB TP2 PWM drive signal
OC TP3 Overcurrent
FC_RC TP4 Filtered return current
+15V TP5 Power
GND TP6 GND
SMAC TP7 PWM control voltage