Schweitzer Engineering Laboratories SEL-421-4, Instruction Manual

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11.56
SEL-421 Relay Instruction Manual Date Code 20171021
Relay Word Bits
Row Lists
209 TSYNCA Assert while the time mark from time source or fixed internal source is not synchronized
209 TSOK Assert if current time source accuracy is sufficient for synchronized phasor measurements
209 PMDOK Assert if data acquisition system is operating correctly
209 UPD_EN Asserts when updating of the internal clock with the selected external time source is enabled
210 FREQOK Assert if relay is estimating frequency
210 FREQFZ Assert if relay is not estimating frequency
210 TSYNC Asserts when the ADC sampling is synchronized to an IRIG-B time source
210 BLKLPTS Asserts when the relay blocks a low-priority time source from updating the relay time
210 TLOCAL Asserts when the relay internal clock and ADC sampling are synchronized to a non-C37.118
compliant high-accuracy IRIG-B time source
210 TPLLEXT Asserts when the phase-locked loop (PLL) is updating from an external time source
210 TSSW Asserts when high-priority time source switching is in progress
210 TGLOBAL Asserts when the relay internal clock and ADC sampling are synchronized to a C37.118-com-
pliant high-accuracy IRIG-B time source
211 TPTP Time is based on a valid PTP source
211 TBNC Time is based on a valid BNC IRIG-B source
211 TSER Time is based on a valid Serial IRIG-B source
211 * Reserved
212 SER_SET Asserts when the serial IRIG-B source is the qualified high-accuracy time source
212 SER_RST Asserts when the serial IRIG-B source is disqualified as the high-accuracy time source
212 BNC_SET Asserts when the BNC IRIG-B source is the qualified high-accuracy time source
212 BNC_RST Asserts when the BNC IRIG-B source is disqualified as the high-accuracy time source
212 BNC_OK Asserts when an IRIG-B signal of sufficient quality is available from the BNC port
212 SER_OK Asserts when an IRIG-B signal of sufficient quality is available from serial Port 1
212 UPD_BLK Asserts when the relay blocks the updating of the internal clock period and Master Time
212 BNC_BNP Asserts for excessive jitter on the BNC port, resulting in the loss of the IRIG-B signal
213 SER_BNP Asserts for excessive jitter on the serial port, resulting in the loss of the IRIG-B signal
213 BNC_TIM Asserts when a valid IRIG-B time source is detected on the BNC port
213 SER_TIM Asserts when a valid IRIG-B time source is detected on the serial port
213 SERSYNC Synchronized to a high quality serial IRIG-B source
213 BNCSYNC Synchronized to a high quality BNC IRIG-B source
213 * Reserved
213 * Reserved
213 * Reserved
Table 11.39 Relay Word Bits: Pushbuttons and Outputs (Sheet 1 of 2)
Row Name Description
214 PB1–PB8 Pushbutton 1–8
215 OUT101–OUT108 Main Board Output 1–8
216 OUT201–OUT208 Optional I/O Board 1 Output 1–8
217 OUT209–OUT216 Optional I/O Board 1 Output 9–16
Table 11.38 Relay Word Bits: Time and Date Management and Frequency Estimation (Sheet 2 of 2)
Row Name Description