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Keysight InfiniiVision M9241/42/43A PXIe Oscilloscopes SCPI Programmer's Guide
37
Status Reporting
• To monitor an event, first clear the event; then, enable the event. All of the
events are cleared when you initialize the instrument.
• To allow a service request (SRQ) interrupt to an external controller, enable at
least one bit in the Status Byte Register (by setting, or unmasking, the bit in the
Service Request Enable register).
The Status Byte Register, the Standard Event Status Register group, and the
Output Queue are defined as the Standard Status Data Structure Model in IEEE
488.2-1987.
The bits in the status byte act as summary bits for the data structures residing
behind them. In the case of queues, the summary bit is set if the queue is not
empty. For registers, the summary bit is set if any enabled bit in the event register
is set. The events are enabled with the corresponding event enable register. Events
captured by an event register remain set until the register is read or cleared.
Registers are read with their associated commands. The *CLS command clears all
event registers and all queues except the output queue. If you send *CLS
immediately after a program message terminator, the output queue is also
cleared.
Overload
Event
Register
Overload
Event
Enable
Register
Arm Event
Register
RUN
Bit
Operation
Status
Condition/
Event
Registers
Operation
Status
Enable
Register
.BTL
Trigger Event
Register
Output
Queue
Standard
Event
Status
Enable
Register
(Mask)
Message
Queue
Standard
Event
Status
Register
Error
Queue
Status
Byte
Register
Service
Request
Enable
Register
Service
Request
Generation
Service
Request (SRQ)
Interrupt
to Computer
(Mask)
Hardware
Event
Condition/
Event Register
Hardware
Event
Enable
Register
Mask Test
Event
Register
Mask Test
Event
Enable
Register