Hitachi H8S/2670, Reference Manual

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4.7 Idle Cycle
4.7.1 Operation
When the H8S/2678 Series chip accesses external space, it can insert an idle cycle (T
i
) between
bus cycles in the following two cases: (1) when read accesses in different areas occur
consecutively, and (2) when a write cycle occurs immediately after a read cycle. Insertion of a 1-
state or 2-state idle cycle can be selected with the IDLC bit in the BCR register.
By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, etc.,
with a long output floating time, and high-speed memory, I/O interfaces, and so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in the BCR register, an idle cycle is inserted at the start of the second read
cycle.
Figure 4.44 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
T
1
Address bus
ø
RD
Bus cycle A
; y
Data bus
T
2
T
3
T
1
T
2
Bus cycle B
Long output
floating time
Data
collision
(a) Idle cycle not inserted
(ICIS1 = 0)
T
1
Address bus
ø
RD
Bus cycle A
Data bus
T
2
T
3
T
i
T
1
Bus cycle B
(b) Idle cycle inserted
(ICIS1 = 1 (initial value))
T
2
CS
(area A)
CS
(area B)
CS
(area A)
CS
(area B)
Figure 4.44 Example of Idle Cycle Operation (1)
(Consecutive Reads in Different Areas)