Hitachi H8S/2670, Reference Manual

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Section 3 Exception Handling and Interrupt Controller
3.1 Overview
3.1.1 Exception Handling Types and Priority
As table 3.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 3.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions
are accepted at all times in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on
the interrupt control mode set by the INTM0 and INTM1 bits in INTCR.
For details of exception handling and the interrupt controller, see section 2, Exception Handling,
and section 3, Interrupt Controller, in the H8S/2678 Series Hardware Manual.
Table 3.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts after a low-to-high transition at the
RES
pin, or
when the watchdog timer overflows
Trace
*
1
Starts when execution of the current instruction or
exception handling ends, if the trace (T) bit is set to 1
Interrupt Starts when execution of the current instruction or
exception handling ends, if an interrupt request has
been issued
*
2
Low Trap instruction *
3
(TRAPA) Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in the program
execution state.