327
5.19.13
Port E
PEn
R
PEnPCR
C
Q
D
Reset
All areas 8-bit access space
External
data write
Modes
1, 2, 4, 5, 6
Mode 7
All areas 8-bit
access space
Mode 7
WPCRE
RPCRE
R
PEnDDR
C
Q
D
Reset
WDDRE
PEnDR
C
Q
D
Reset
WDRE
RDRE
RPORE
WDDRE: Write to PEDDR
WDRE:
Write to PEDR
WPCRE: Write to PEPCR
RPORE: Read port E
RDRE: Read
PEDR
RPCRE: Read
PEPCR
n = 0 to 7
Note:
*
Output enable signal
*
External data
lower read
R
System controller
EXPE
Internal upper data bus
Internal lower data bus
Figure 5.49 Port E Block Diagram (Pins PEn)
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