Hitachi H8S/2670, Reference Manual

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TCSR0—Timer Control/Status Register 0 H'FFB2 8-Bit Timer Channel 0
TCSR1—Timer Control/Status Register 1 H'FFB3 8-Bit Timer Channel 1
Bit
Initial value
Read/Write
TCSR0
7
CMFB
0
R/(W) *
6
CMFA
0
R/(W) *
5
OVF
0
R/(W) *
4
ADTE
0
R/W
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
Bit
Initial value
Read/Write
TCSR1 7
CMFB
0
R/(W)
*
6
CMFA
0
R/(W)
*
5
OVF
0
R/(W)
*
4
—
1
—
3
OS3
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
0
OS0
0
R/W
Output Select
0 No change when compare match A occurs
1
0
1
0
1
0 is output when compare match A occurs
1 is output when compare match A occurs
Output is inverted when compare match A
occurs (toggle output)
Output Select
0 No change when compare match B occurs
1
0
1
0
1
0 is output when compare match B occurs
1 is output when compare match B occurs
Output is inverted when compare match B
occurs (toggle output)
A/D Trigger Enable (TCSR0 only)
0 A/D converter start requests by compare match A are disabled
1 A/D converter start requests by compare match A are enabled
Timer Overflow Flag
0 [Clearing condition]
When 0 is written to OVF after reading OVF = 1
1 [Setting condition]
When TCNT overflows (from H'FF to H'00)
Compare Match Flag A
0 [Clearing conditions]
• When 0 is written to CMFA after reading CMFA = 1
• When the DTC is activated by a CMIA interrupt, and the DISEL bit in the DTC’s MRB register is 0
1 [Setting condition]
When TCNT = TCORA
Compare Match Flag B
0 [Clearing conditions]
• When 0 is written to CMFB after reading CMFB = 1
• When the DTC is activated by a CMIB interrupt, and the DISEL bit in the DTC’s MRB register is 0
1 [Setting condition]
When TCNT = TCORB
Note: * Only 0 can be written to bits 7 to 5, to clear the flags.