Hitachi H8S/2670, Reference Manual

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114
Bit 15
CMF
Description
0 [Clearing conditions]
•
When 0 is written to CMF after reading CMF = 1 while the RFSHE bit is cleared to
0 (Initial value)
•
When CBR refreshing is executed while the RFSHE bit is set to 1
1 [Setting condition]
When RTCOR = RTCNT
Bit 14—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests
(CMI) by the CMF flag when the CMF flag is set to 1.
This bit is valid only when refresh control is not performed (when the RFSHE bit is cleared to 0).
When the RFSHE bit is set to 1 and refresh control is performed, the CMIE bit is always cleared to
0 and cannot be modified.
Bit 14
CMIE
Description
0 Interrupt request by CMF flag disabled (Initial value)
1 Interrupt request by CMF flag enabled
Bits 13 and 12—
CAS
-
RAS
Wait Control (RCW1, RCW0): These bits select whether or not a
wait cycle is to be inserted between the
CAS
assert cycle and
RAS
assert cycle in a DRAM refresh
cycle. A 1- to 3-state wait cycle can be inserted.
Bit 13
RCW1 Bit 12
RCW0
Description
0 0 Wait state not inserted between
CAS
and
RAS
in refresh cycle
(Initial value)
1 1 wait state inserted between
CAS
and
RAS
in refresh cycle
1 0 2 wait states inserted between
CAS
and
RAS
in refresh cycle
1 3 wait states inserted between
CAS
and
RAS
in refresh cycle
Bit 11—Reserved: This is a readable/writable bit, but the write value should always be 0.
Bits 10 to 8—Refresh Counter Clock Select (RTCK2 to RTCK0): These bits select the clock to
be used to increment the refresh counter from among seven internal clocks obtained by dividing
the system clock (ø).
When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting
up.