Hitachi H8S/2670, Reference Manual

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4.4 Basic Bus Interface
4.4.1 Overview
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, and
CSACR. For details see table 4.3.
4.4.2 Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 4.7 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word access is performed as two byte accesses,
and a longword access, as four byte accesses.
D15 D8 D7 D0
Upper data bus Lower data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 4.7 Access Sizes and Data Alignment Control (8-Bit Access Space)