Hitachi H8S/2670, Reference Manual

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When area 7 external space is accessed, the
CS7
signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
4.3.4 Chip Select Signals
The chip can output chip select signals (
CS0
to
CS7
) for areas 0 to 7, the signal being driven low
when the corresponding external space area is accessed.
Figure 4.6 shows an example of
CSn
(n = 0 to 7) output timing.
Enabling or disabling of
CSn
signal output is performed by setting the data direction register
(DDR) bit for the port corresponding to the particular
CSn
pin.
In expanded mode with on-chip ROM disabled, the
CS0
pin is placed in the output state after a
reset. Pins
CS1
to
CS7
are placed in the input state after a reset and so the corresponding DDR bits
should be set to 1 when outputting signals
CS1
to
CS7
.
In expanded mode with on-chip ROM enabled, pins
CS0
to
CS7
are all placed in the input state
after a reset and so the corresponding DDR bits should be set to 1 when outputting signals
CS0
to
CS7
.
For details see section 5, I/O Ports.
When areas 2 to 5 are designated as DRAM space, outputs
CS2
to
CS5
are used as
RAS
signals.
Bus cycle
T
1
T
2
T
3
Area n external address Address bus
ø
CSn
Figure 4.6
CSn
Signal Output Timing (n = 0 to 7)