Hitachi H8S/2670, Reference Manual

Page: 196 / 647

179
4.10 Bus Arbitration
4.10.1 Overview
The H8S/2678 Series has a bus arbiter that arbitrates bus master operations.
There are four bus masters—the CPU, DTC, DMAC, and EXDMAC—that perform read/write
operations when they have possession of the bus. Each bus master requests the bus by means of a
bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use
of the bus by means of a bus request acknowledge signal. The selected bus master then takes
possession of the bus and begins its operation.
4.10.2 Operation
The bus arbiter monitors the bus masters’ bus request signals, and if the bus is requested, sends a
bus request acknowledge signal to the bus master making the request. If there are bus requests
from more than one bus master, the bus request acknowledge signal is sent to the one with the
highest priority. When a bus master receives the bus request acknowledge signal, it takes
possession of the bus until that signal is canceled.
The order of priority of the bus masters is as follows:
(High) EXDMAC > DMAC > DTC > CPU (Low)
An external access by an internal bus master (except the EXDMAC) and (1) external bus release,
(2) a refresh when the CBRM bit is 0, and (3) an external bus access by the EXDMAC can be
executed in parallel.
If an external bus release request, a refresh request, and an external access by an internal bus
master occur simultaneously, the order of priority is as follows:
(High) Refresh > EXDMAC > External bus release (Low)
(High) External bus release > External access by internal bus master except EXDMAC (Low)
As a refresh when the CBRM bit is 0 and an external access other than to DRAM space by an
internal bus master can be executed simultaneously, there is no relative order of priority for these
two operations.