Hitachi H8S/2670, Reference Manual

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4.5.3 Address Multiplexing
With DRAM space, the row address and column address are multiplexed. In address multiplexing,
the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table
4.6 shows the correspondence between the settings of MXC2 to MXC0 and the shift size.
Table 4.6 Address Multiplexing Settings by Bits MXC2 to MXC0
DRAMCR Address Pins
MXC2 MXC1 MXC0 Shift Size
A23
to
A16 A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Row
address 0 0 0 8 bits A23
to
A16 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
1 9 bits A23
to
A16 A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
1 0 10 bits A23
to
A16 A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
1 11 bits A23
to
A16 A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
1 — — Reserved
(setting
prohibited) — — — — — — — — — — — — — — — — —
Column
address — — — — A23
to
A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
4.5.4 Data Bus
If a bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space,
×
16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D15 to D0, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 4.4.2, Data
Size and Data Alignment.