Hitachi H8S/2670, Reference Manual

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Table 1.1 Overview
Item Specifications
CPU
•
General-register architecture

Sixteen 16-bit general registers (also usable as sixteen 8-bit registers
or eight 32-bit registers)
•
High-speed operation suitable for realtime control

Maximum operating frequency: 33 MHz

High-speed arithmetic operations
8/16/32-bit register-register add/subtract: 30 ns (33 MHz operation)
16
×
16-bit register-register multiply: 90 ns (33 MHz operation)
32 ÷ 16-bit register-register divide: 600 ns (33 MHz operation)
•
Instruction set suitable for high-speed operation

Sixty-five basic instructions

8/16/32-bit transfer/arithmetic and logic instructions

Unsigned/signed multiply and divide instructions

Powerful bit-manipulation instructions
•
CPU operating mode

Advanced mode: 16-Mbyte address space
Bus controller
•
Address space divided into 8 areas, with bus specifications settable
independently for each area
•
Chip select output possible for each area
•
Selection of 8-bit or 16-bit access space for each area
•
2-state or 3-state access space can be designated for each area
•
Number of program wait states can be set for each area
•
Maximum 8-Mbyte DRAM directly connectable
(or use of interval timer possible)
•
External bus release function
DMA controller
(DMAC)
•
Selection of short address mode or full address mode
•
Four channels in short address mode, two channels in full address mode
•
Transfer possible in repeat mode, block transfer mode, etc.
•
Single address mode transfer possible
•
Can be activated by internal interrupt