Hitachi H8S/2670, Reference Manual

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4.2.4 Read Strobe Timing Control Register (RDNCR)................................................. 99
4.2.5
CS
Assertion Period Control Registers (CSACRH, CSACRL) ........................... 101
4.2.6 Area 0 Burst ROM I/F Control Register (BROMCRH)
Area 1 Burst ROM I/F Control Register (BROMCRL) ....................................... 103
4.2.7
Bus Control Register (BCR)................................................................................. 105
4.2.8 DRAM Control Register (DRAMCR).................................................................. 107
4.2.9 DRAM Access Control Register (DRACCR) ...................................................... 112
4.2.10 Refresh Control Register (REFCR) ...................................................................... 113
4.2.11 Refresh Timer Counter (RTCNT) ........................................................................ 117
4.2.12 Refresh Time Control Register (RTCOR)............................................................ 117
4.3 Overview of Bus Control................................................................................................... 118
4.3.1 Area
Division........................................................................................................ 118
4.3.2 Bus Specifications ................................................................................................ 119
4.3.3 Memory Interfaces................................................................................................ 120
4.3.4 Chip Select Signals............................................................................................... 122
4.4 Basic Bus Interface ............................................................................................................ 123
4.4.1 Overview............................................................................................................... 123
4.4.2
Data Size and Data Alignment ............................................................................. 123
4.4.3 Valid Strobes ........................................................................................................ 124
4.4.4 Basic Timing......................................................................................................... 126
4.4.5 Wait Control ......................................................................................................... 134
4.4.6 Read Strobe (
RD
) Timing..................................................................................... 136
4.4.7 Extension of Chip Select (
CS
) Assertion Period .................................................. 137
4.5 DRAM Interface ................................................................................................................ 138
4.5.1 Overview............................................................................................................... 138
4.5.2
Setting DRAM Space ........................................................................................... 138
4.5.3 Address Multiplexing ........................................................................................... 139
4.5.4 Data Bus ............................................................................................................... 139
4.5.5 Pins Used for DRAM Interface ............................................................................ 140
4.5.6 Basic Timing......................................................................................................... 141
4.5.7 Column Address Output Cycle Control ............................................................... 142
4.5.8 Row Address Output Cycle Control..................................................................... 143
4.5.9 Precharge State Control ........................................................................................ 145
4.5.10 Wait Control ......................................................................................................... 146
4.5.11 Byte Access Control ............................................................................................. 149
4.5.12 Burst
Operation..................................................................................................... 150
4.5.13 Refresh Control..................................................................................................... 154
4.5.14 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface .... 159
4.6 Burst ROM Interface ......................................................................................................... 162
4.6.1 Overview............................................................................................................... 162
4.6.2 Basic
Timing......................................................................................................... 162
4.6.3 Wait Control ......................................................................................................... 164
4.6.4 Write Access......................................................................................................... 164