35
Writing of 0 to EXPE when its value is 1 should only be carried out when an external bus cycle* is
not being executed.
Note: * There are cases where external and internal bus cycles are executed in parallel due to the
write data buffer function, the refresh control function, the EXDMAC, the bus-released
state, and so forth.
Bit 1
EXPE
Description
0
External bus disabled
1
External bus enabled
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM disabled
1
On-chip RAM enabled
(Initial value)
2.3
Operating Mode Descriptions
2.3.1
Mode 1 (Expanded Mode with On-Chip ROM Disabled)
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, ports D and E function as a data bus, and parts of
ports F and G carry bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access
is designated for all areas by the bus controller, the bus mode switches to 8 bits.
2.3.2
Mode 2 (Expanded Mode with On-Chip ROM Disabled)
This is an externally expanded mode with on-chip ROM disabled.
Operation is the same as in mode 1, except that the initial external bus mode after a reset is 8 bits.
2.3.3
Mode 3
This mode is not supported in the H8S/2678 Series, and must not be selected.
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