Hitachi H8S/2670, Reference Manual

Page: 613 / 647

596
SSR2—Serial Status Register 2 H'FF8C Smart Card Interface 2
Bit
Initial value
Read/Write
7
TDRE
1
R/(W) *
6
RDRF
0
R/(W) *
5
ORER
0
R/(W) *
4
ERS
0
R/(W) *
3
PER
0
R/(W) *
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
0
Multiprocessor Bit Transfer
1
0
Multiprocessor Bit
1
0
Transmit End
1
0
Transmit Data Register Empty
1
Note: * Can only be written with 0, to clear the flag.
0
Receive Data Register Full
1
0
Overrun Error
1
0
Error Signal Status
1
0
Parity Error
1
Note: etu (Elementary Time Unit): Time for transfer of 1 bit
Data with a 0 multiprocessor bit
is transmitted
Data with a 1 multiprocessor bit
is transmitted
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
Transmission is in progress
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/
E
bit in SMR
Data received normally—no error signal
[Clearing conditions]
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
Error signal has been sent from receiving device, indicating parity error detection
[Setting condition]
When the low level of the error signal is sampled
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC or DTC is activated by an RXI interrupt and reads data from RDR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state.
Transmission has ended
[Setting conditions]
• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after transmission
of a 1-byte serial character when GM = 0 and BLK = 0
• When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after transmission
of a 1-byte serial character when GM = 0 and BLK = 1
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission
of a 1-byte serial character when GM = 1 and BLK = 0
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after transmission
of a 1-byte serial character when GM = 1 and BLK = 1