Hitachi H8S/2670, Reference Manual

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143
4.5.8 Row Address Output Cycle Control
If the RAST bit is set to 1 in the DRAMCR register, the
RAS
signal goes low from the beginning
of the T
r
state, and the row address hold time and DRAM read access time are changed relative to
the fall of the
RAS
signal. Use the optimum setting according to the DRAM connected and the
operating frequency of the chip. Figure 4.22 shows an example of the timing when the
RAS
signal
goes low from the beginning of the T
r
state.
T
p
ø
RASn
(
CSn
)
Read
Write
UCAS
,
LCAS
WE
(
HWR
)
OE
(
RD
)
Data bus
WE
(
HWR
)
OE
(
RD
)
Data bus
Address bus
T
r
T
c1
T
c2
Row address Column address
High
High
Note: n = 2 to 5
Figure 4.22 Example of Access Timing when
RAS
Signal Goes Low from Beginning
of T
r
State (CAST = 0)