Hitachi H8S/2670, Reference Manual

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Port G Data Register (PGDR)
Bit 7 6 5 4 3 2 1 0
— PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR
Initial value 0 0 0 0 0 0 0 0
Read/Write — R/W R/W R/W R/W R/W R/W R/W
PGDR is a 7-bit readable/writable register that stores output data for the port G pins (PG6 to PG0).
Bit 7 is reserved; it is always read as 0, and cannot be modified.
PGDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode.
Port G Register (PORTG)
Bit 7 6 5 4 3 2 1 0
— PG6 PG5 PG4 PG3 PG2 PG1 PG0
Initial value Undefined — * — * — * — * — * — * — *
Read/Write R R R R R R R R
Note:
*
Determined by the state of pins PG6 to PG0.
PORTG is a 7-bit read-only register that shows the pin states. PORTG cannot be written to;
writing of output data for the port G pins (PG6 to PG0) must always be performed on PGDR.
Bit 7 is reserved; if read it will return an undefined value.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTG contents are determined by the pin states, as
PGDDR and PGDR are initialized. PORTG retains its prior state in software standby mode.
Port Function Control Register 0 (PFCR0)
Bit 7 6 5 4 3 2 1 0
CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
PFCR0 is an 8-bit readable/writable register that performs I/O port control. PFCR0 is initialized to
H'FF by a reset and in hardware standby mode. It retains its prior state in software standby mode.