Hitachi H8S/2670, Reference Manual

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When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single
address transfer mode, full access (normal access) is always performed. With the DRAM interface,
the
DACK
or
EDACK
output goes low from the T
r
state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing DRAM space.
Figure 4.41 shows the
DACK
/
EDACK
output timing for the DRAM interface when DDS = 0 or
EDDS = 0.
T
p
ø
RASn
(
CSn
)
Read
Write
UCAS
,
LCAS
WE
(
HWR
)
OE
(
RD
)
Data bus
WE
(
HWR
)
OE
(
RD
)
Data bus
DACK
or
EDACK
Address bus
T
r
T
c1
T
c2
Note: n = 2 to 5
T
c3
Row address Column address
High
High
Figure 4.41 Example of
DACK
/
EDACK
Output Timing when DDS = 0 or EDDS = 0 (2)
(RAST = 0, CAST = 1)