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Section 4 Bus Controller
4.1
Overview
The H8S/2678 Series has an on-chip bus controller (BSC) that manages the external address space
divided into eight areas. The bus specifications, such as bus width and number of access states,
can be set independently for each area, enabling multiple memories and external I/O devices to be
connected easily.
The bus controller also has a bus arbitration function, and controls the operation of the internal bus
masters—the CPU, DMA controller (DMAC), data transfer controller (DTC), and external bus
transfer DMAC (EXDMAC).
4.1.1
Features
The features of the bus controller are listed below.
•
Manages external address space in area units
Manages the external space as eight areas of 2 Mbytes
Bus specifications can be set independently for each area
8-bit access or 16-bit access can be selected for each area
DRAM and burst ROM interfaces can be set
•
Basic bus interface
Chip select signals (
CS0
to
CS7
) can be output for areas 0 to 7
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
CS
assertion period extension states can be inserted for each area
•
DRAM interface
DRAM interface can be set for areas 2 to 5
Row address/column address multiplexed output (8/9/10/11 bits)
2-CAS access method for byte control
Burst operation using fast page mode
T
P
cycle insertion to secure RAS precharging time
Selection of CAS-before-RAS (CBR) refreshing or self-refreshing
OE
signal can be output
Continuous DRAM space can be designated for areas 2 to 5
•
Burst ROM interface
Burst ROM interface can be set for area 0 and area 1
Area 0 and area 1 burst ROM interfaces can be set independently
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