Hitachi H8S/2670, Reference Manual

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4.9.2 Operation
In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in the BCR register. Driving the
BREQ
pin low issues an external bus request to the
H8S/2678 Series chip. When the
BREQ
pin is sampled, at the prescribed timing the
BACK
pin is
driven low, and the address bus, data bus, and bus control signals are placed in the high-
impedance state, establishing the external bus released state.
In the external bus released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers initiation
of the bus cycle, and waits for the bus request from the external bus master to be canceled. If a
refresh request is generated in the external bus released state, or if a SLEEP instruction is executed
to place the chip in software standby mode or all-module-clocks-stopped mode, refresh control
and software standby or all-module-clocks-stopped control is deferred until the bus request from
the external bus master is canceled.
If the BREQOE bit is set to 1 in the BCR register, the
BREQO
signal can be driven low when any
of the following requests are issued, to request cancellation of the bus request externally.
•
When an internal bus master wants to perform an external access
•
When a refresh request is generated
•
When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode
When the
BREQ
pin is driven high, the
BACK
pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is
as follows:
(High) External bus release > External access by internal bus master (Low)
If a refresh request and external bus release request occur simultaneously, the order of priority is
as follows:
(High) Refresh > External bus release (Low)