Hitachi H8S/2670, Reference Manual

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110
Bit 6—
RAS
Down Mode (RCDM): When access to DRAM space is interrupted by an access to
normal bus space, an access to an internal I/O register, etc., this bit selects whether the
RAS
signal
is held low while waiting for the next DRAM access (
RAS
down mode), or is driven high again
(
RAS
up mode).
The setting of this bit is valid only when the BE bit is set to 1.
If this bit is cleared to 0 when set to 1 in the
RAS
down state, the
RAS
down state is cleared at that
point, and
RAS
goes high.
Bit 6
RCDM
Description
0
RAS
up mode selected for DRAM space access (Initial value)
1
RAS
down mode selected for DRAM space access
Bit 5—DMAC Single Address Transfer Option (DDS): Specifies whether full access is always
performed or burst access is enabled when DMAC single address transfer is performed on the
DRAM interface.
When the BE bit is cleared to 0 in DRAMCR, disabling DRAM burst access, DMAC single
address transfer is performed in full access mode regardless of the setting of the DDS bit.
This bit has no effect on other bus master external accesses or DMAC dual address transfers.
Bit 5
DDS
Description
0 Full access is always executed when DMAC single address transfer is performed in
DRAM space
(Initial value)
1 Burst access is possible when DMAC single address transfer is performed in DRAM
space
Bit 4—EXDMAC Single Address Transfer Option (EDDS): Specifies whether full access is
always performed or burst access is enabled when EXDMAC single address transfer is performed
on the DRAM interface.
When the BE bit is cleared to 0 in DRAMCR, disabling DRAM burst access, EXDMAC single
address transfer is performed in full access mode regardless of the setting of the EDDS bit.
This bit has no effect on other bus master external accesses or EXDMAC dual address transfers.