Hitachi H8S/2670, Reference Manual

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5.11.2 Register Configuration
Table 5.20 shows the port B register configuration.
Table 5.20 Port B Registers
Name Abbreviation R/W Initial Value Address *
Port B data direction register PBDDR W H'00 H'FE2A
Port B data register PBDR R/W H'00 H'FF6A
Port B register PORTB R Undefined H'FF5A
Port B MOS pull-up control register PBPCR R/W H'00 H'FE37
Note:
*
Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
Bit 7 6 5 4 3 2 1 0
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value 0 0 0 0 0 0 0 0
Read/Write W W W W W W W W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
•
Modes 1, 2, 5, and 6
Port B pins are address outputs regardless of the PBDDR settings.
•
Mode 4
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing
the bit to 0 makes the pin an input port.
•
Mode 7 (when bit EXPE is set to 1 in SYSCR)
Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing
the bit to 0 makes the pin an input port.
•
Mode 7 (when bit EXPE is cleared to 0 in SYSCR)
Port B is an I/O port, and its pin functions can be switched with PBDDR.