Hitachi H8S/2670, Reference Manual

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159
DRAM space write
T
rc3
T
rp1
T
rp2
T
p
T
r
Software
standby
T
c1
T
c2
Note: n = 2 to 5
ø
RASn
(
CSn
)
UCAS
,
LCAS
OE
(
RD
)
WR
(
HWR
)
Data bus
Address bus
Figure 4.39 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States
Refreshing and All-Module-Clocks-Stopped Mode: In the H8S/2678 Series, if the ACSE bit is
set to 1 in the MSTPCR register, and then a SLEEP instruction is executed with the setting for all
supporting module clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer
module alone (MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-
clocks-stopped mode is entered, in which the bus controller and I/O port clocks are also stopped.
As the bus controller clock is also stopped in this mode, CBR refreshing is not executed. If DRAM
is connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be
cleared to 0 in MSTPCR.
4.5.14 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
When burst mode is selected on the DRAM interface, the
DACK
and
EDACK
output timing can
be selected with the DDS and EDDS bits. When DRAM space is accessed in DMAC/EXDMAC
single address mode at the same time, these bits select whether or not burst access is to be
performed.