Hitachi H8S/2670, Reference Manual

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4.2 Register Descriptions
4.2.1 Bus Width Control Register (ABWCR)
Bit 7 6 5 4 3 2 1 0
ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0
Modes 2, 4, 6
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Modes 1, 5, 7
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
ABWCR is an 8-bit readable/writable register that designates each area as either 8-bit access space
or 16-bit access space.
ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers is fixed regardless of the settings in ABWCR.
After a reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 2, 4, and 6,
and to H'00 in modes 1, 5, and 7. It is not initialized in software standby mode.
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the
corresponding area is to be designated as 8-bit access space or 16-bit access space.
Bit n
ABWn
Description
0 Area n is designated as 16-bit access space
1 Area n is designated as 8-bit access space
(n = 7 to 0)
4.2.2 Access State Control Register (ASTCR)
Bit 7 6 5 4 3 2 1 0
AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
Initial value 1 1 1 1 1 1 1 1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
ASTCR is an 8-bit readable/writable register that designates each area as either 2-state access
space or 3-state access space.