Hitachi H8S/2670, Reference Manual

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4.5 DRAM Interface
4.5.1 Overview
In the H8S/2678 Series, external space areas 2 to 5 can be designated as DRAM space, and
DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to the
chip. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in
DRAMCR. Burst operation is also possible, using fast page mode.
4.5.2 Setting DRAM Space
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in the DRAMCR
register. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown
in table 4.5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four
areas (areas 2 to 5), and continuous area (areas 2 to 5).
Table 4.5 DRAM Space Settings by Bits RMTS2 to RMTS0
RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2
0 0 1 Normal space Normal space Normal space DRAM space
1 0 Normal space Normal space DRAM space DRAM space
1 DRAM space DRAM space DRAM space DRAM space
1 0
*
Reserved Reserved Reserved Reserved
1 0
(setting
prohibited) (setting
prohibited) (setting
prohibited) (setting
prohibited)
1 Continuous
DRAM space Continuous
DRAM space Continuous
DRAM space Continuous
DRAM space
* : Don’t care
With continuous DRAM space,
RAS2
is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.