Hitachi H8S/2670, Reference Manual

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The H8S/2678 Series mask ROM version can be used only in modes 1, 2, and 4 to 7, and the
ROMless version only in modes 1 and 2. This means that the mode pins must be set to select one
of these modes.
Do not change the inputs at the mode pins during operation.
2.1.3 Register Configuration
The H8S/2678 Series has a mode control register (MDCR) that indicates the inputs at the mode
pins (MD2 to MD0), and a system control register (SYSCR) that controls the operation of the
chip. Table 2.3 summarizes these registers.
Table 2.3 Registers
Name Abbreviation R/W Initial Value Address *
1
Mode control register MDCR R Undefined H'FF3E
System control register SYSCR R/W H'C1/H'C3 *
2
H'FF3D
Notes: 1. Lower 16 bits of the address.
2. Determined by pins MD2 to MD0.
2.2 Register Descriptions
2.2.1 Mode Control Register (MDCR)
Bit 7 6 5 4 3 2 1 0
— — — — — MDS2 MDS1 MDS0
Initial value 0 0 0 0 0 —
*
—
*
—
*
Read/Write — — — — — R R R
Note:
*
Determined by pins MD2 to MD0.
MDCR is an 8-bit read-only register that monitors the current operating mode of the H8S/2678
Series chip.
Bits 7 to 3—Reserved: These bits are always read as 0 and cannot be modified. The write value
should always be 1.
Bits 2 to 0—Mode Select 2 to 0 (MD2 to MD0): These bits indicate the input levels at pins MD2
to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD2 to MD0.
MDS2 to MDS0 are read-only bits—they cannot be written to. The mode pin (MD2 to MD0) input
levels are latched into these bits when MDCR is read. These latches are canceled by a reset.