Hitachi H8S/2670, Reference Manual

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16-Bit Access Space: Figure 4.8 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
D15 D8 D7 D0
Upper data bus Lower data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
• Even address
Byte size • Odd address
Figure 4.8 Access Sizes and Data Alignment Control (16-bit Access Space)
4.4.3 Valid Strobes
Table 4.4 shows the data buses used and valid strobes for the access spaces.
In a read, the
RD
signal is valid for both the upper and the lower half of the data bus.
In a write, the
HWR
signal is valid for the upper half of the data bus, and the
LWR
signal for the
lower half.