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Registers
368
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.7 INTC_CLKC_CONTROL Registers
lists the memory-mapped registers for the INTC_CLKC_CONTROL. All register offset
addresses not listed in
should be considered as reserved locations and the register contents
should not be modified.
Table 1-167. INTC_CLKC_CONTROL REGISTERS
Offset
Acronym
Register Name
Section
0h
pid
PID Register
10h
sysconfig
SYS Config Register
20h
intc_intr0_status_raw0
Interrupt0 Raw Register 0
24h
intc_intr0_status_raw1
Interrupt0 Raw Register 1
28h
intc_intr0_status_ena0
Interrupt0 Enabled Register 0
2Ch
intc_intr0_status_ena1
Interrupt0 Enabled Register 1
30h
intc_intr0_ena_set0
Interrupt0 Enable/Set Register 0
34h
intc_intr0_ena_set1
Interrupt0 Enable/Set Register 1
38h
intc_intr0_ena_clr0
Interrupt0 Enable/Clear Register 0
3Ch
intc_intr0_ena_clr1
Interrupt0 Enable/Clear Register 1
40h
intc_intr1_status_raw0
Interrupt1 Raw Register 0
44h
intc_intr1_status_raw1
Interrupt1 Raw Register 1
48h
intc_intr1_status_ena0
Interrupt1 Enabled Register 0
4Ch
intc_intr1_status_ena1
Interrupt1 Enabled Register 1
50h
intc_intr1_ena_set0
Interrupt1 Enable/Set Register 0
54h
intc_intr1_ena_set1
Interrupt1 Enable/Set Register 1
58h
intc_intr1_ena_clr0
Interrupt1 Enable/Clear Register 0
5Ch
intc_intr1_ena_clr1
Interrupt1 Enable/Clear Register 1
60h
intc_intr2_status_raw0
Interrupt2 Raw Register 0
64h
intc_intr2_status_raw1
Interrupt2 Raw Register 1
68h
intc_intr2_status_ena0
Interrupt2 Enabled Register 0
6Ch
intc_intr2_status_ena1
Interrupt2 Enabled Register 1
70h
intc_intr2_ena_set0
Interrupt2 Enable/Set Register 0
74h
intc_intr2_ena_set1
Interrupt2 Enable/Set Register 1
78h
intc_intr2_ena_clr0
Interrupt2 Enable/Clear Register 0
7Ch
intc_intr2_ena_clr1
Interrupt2 Enable/Clear Register 1
80h
intc_intr3_status_raw0
Interrupt3 Raw Register 0
84h
intc_intr3_status_raw1
Interrupt3 Raw Register 0
88h
intc_intr3_status_ena0
Interrupt3 Enabled Register 0
8Ch
intc_intr3_status_ena1
Interrupt3 Enabled Register 1
90h
intc_intr3_ena_set0
Interrupt3 Enable/Set Register 0
94h
intc_intr3_ena_set1
Interrupt3 Enable/Set Register 1
98h
intc_intr3_ena_clr0
Interrupt3 Enable/Clear Register 0
9Ch
intc_intr3_ena_clr1
Interrupt3 Enable/Clear Register 1
A0h
intc_eoi
End of Interrupt Register
100h
clkc_clken
Clock Enable Register
104h
clkc_rst
Soft Reset Register
108h
clkc_dps
Main Datapath Select Register
10Ch
clkc_vip1dps
VIP1 Datapath Select Register
110h
clkc_vip2dps
VIP2 Datapath Select Register
114h
clkc_venc_clksel
VENC Clock Select Register
118h
clkc_venc_ena
VENC Enable Register
11Ch
clkc_range_map
VC1 Range Map Register