Texas Instruments DM38x DaVinci, User Manual

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Registers
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368 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.7 INTC_CLKC_CONTROL Registers
Table 1-167 lists the memory-mapped registers for the INTC_CLKC_CONTROL. All register offset
addresses not listed in Table 1-167 should be considered as reserved locations and the register contents
should not be modified.
Table 1-167. INTC_CLKC_CONTROL REGISTERS
Offset Acronym Register Name Section
0h pid PID Register Section 1.3.7.1
10h sysconfig SYS Config Register Section 1.3.7.2
20h intc_intr0_status_raw0 Interrupt0 Raw Register 0 Section 1.3.7.3
24h intc_intr0_status_raw1 Interrupt0 Raw Register 1 Section 1.3.7.4
28h intc_intr0_status_ena0 Interrupt0 Enabled Register 0 Section 1.3.7.5
2Ch intc_intr0_status_ena1 Interrupt0 Enabled Register 1 Section 1.3.7.6
30h intc_intr0_ena_set0 Interrupt0 Enable/Set Register 0 Section 1.3.7.7
34h intc_intr0_ena_set1 Interrupt0 Enable/Set Register 1 Section 1.3.7.8
38h intc_intr0_ena_clr0 Interrupt0 Enable/Clear Register 0 Section 1.3.7.9
3Ch intc_intr0_ena_clr1 Interrupt0 Enable/Clear Register 1 Section 1.3.7.10
40h intc_intr1_status_raw0 Interrupt1 Raw Register 0 Section 1.3.7.11
44h intc_intr1_status_raw1 Interrupt1 Raw Register 1 Section 1.3.7.12
48h intc_intr1_status_ena0 Interrupt1 Enabled Register 0 Section 1.3.7.13
4Ch intc_intr1_status_ena1 Interrupt1 Enabled Register 1 Section 1.3.7.14
50h intc_intr1_ena_set0 Interrupt1 Enable/Set Register 0 Section 1.3.7.15
54h intc_intr1_ena_set1 Interrupt1 Enable/Set Register 1 Section 1.3.7.16
58h intc_intr1_ena_clr0 Interrupt1 Enable/Clear Register 0 Section 1.3.7.17
5Ch intc_intr1_ena_clr1 Interrupt1 Enable/Clear Register 1 Section 1.3.7.18
60h intc_intr2_status_raw0 Interrupt2 Raw Register 0 Section 1.3.7.19
64h intc_intr2_status_raw1 Interrupt2 Raw Register 1 Section 1.3.7.20
68h intc_intr2_status_ena0 Interrupt2 Enabled Register 0 Section 1.3.7.21
6Ch intc_intr2_status_ena1 Interrupt2 Enabled Register 1 Section 1.3.7.22
70h intc_intr2_ena_set0 Interrupt2 Enable/Set Register 0 Section 1.3.7.23
74h intc_intr2_ena_set1 Interrupt2 Enable/Set Register 1 Section 1.3.7.24
78h intc_intr2_ena_clr0 Interrupt2 Enable/Clear Register 0 Section 1.3.7.25
7Ch intc_intr2_ena_clr1 Interrupt2 Enable/Clear Register 1 Section 1.3.7.26
80h intc_intr3_status_raw0 Interrupt3 Raw Register 0 Section 1.3.7.27
84h intc_intr3_status_raw1 Interrupt3 Raw Register 0 Section 1.3.7.28
88h intc_intr3_status_ena0 Interrupt3 Enabled Register 0 Section 1.3.7.29
8Ch intc_intr3_status_ena1 Interrupt3 Enabled Register 1 Section 1.3.7.30
90h intc_intr3_ena_set0 Interrupt3 Enable/Set Register 0 Section 1.3.7.31
94h intc_intr3_ena_set1 Interrupt3 Enable/Set Register 1 Section 1.3.7.32
98h intc_intr3_ena_clr0 Interrupt3 Enable/Clear Register 0 Section 1.3.7.33
9Ch intc_intr3_ena_clr1 Interrupt3 Enable/Clear Register 1 Section 1.3.7.34
A0h intc_eoi End of Interrupt Register Section 1.3.7.35
100h clkc_clken Clock Enable Register Section 1.3.7.36
104h clkc_rst Soft Reset Register Section 1.3.7.37
108h clkc_dps Main Datapath Select Register Section 1.3.7.38
10Ch clkc_vip1dps VIP1 Datapath Select Register Section 1.3.7.39
110h clkc_vip2dps VIP2 Datapath Select Register Section 1.3.7.40
114h clkc_venc_clksel VENC Clock Select Register Section 1.3.7.41
118h clkc_venc_ena VENC Enable Register Section 1.3.7.42
11Ch clkc_range_map VC1 Range Map Register Section 1.3.7.43