Registers
643
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.71 VPDMA_int2_list0_int_stat Register (offset = 128h) [reset = 0h]
VPDMA_int2_list0_int_stat is shown in
and described in
Figure 1-371. VPDMA_int2_list0_int_stat Register
31
30
29
28
27
26
25
24
INT_STAT_CONTRO
L_DESCRIPTOR_INT
15
INT_STAT_CONTRO
L_DESCRIPTOR_INT
14
INT_STAT_CONTRO
L_DESCRIPTOR_INT
13
INT_STAT_CONTRO
L_DESCRIPTOR_INT
12
INT_STAT_CONTRO
L_DESCRIPTOR_INT
11
INT_STAT_CONTRO
L_DESCRIPTOR_INT
10
INT_STAT_CONTRO
L_DESCRIPTOR_INT
9
INT_STAT_CONTRO
L_DESCRIPTOR_INT
8
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
23
22
21
20
19
18
17
16
INT_STAT_CONTRO
L_DESCRIPTOR_INT
7
INT_STAT_CONTRO
L_DESCRIPTOR_INT
6
INT_STAT_CONTRO
L_DESCRIPTOR_INT
5
INT_STAT_CONTRO
L_DESCRIPTOR_INT
4
INT_STAT_CONTRO
L_DESCRIPTOR_INT
3
INT_STAT_CONTRO
L_DESCRIPTOR_INT
2
INT_STAT_CONTRO
L_DESCRIPTOR_INT
1
INT_STAT_CONTRO
L_DESCRIPTOR_INT
0
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
15
14
13
12
11
10
9
8
INT_STAT_LIST7_NO
TIFY
INT_STAT_LIST7_CO
MPLETE
INT_STAT_LIST6_NO
TIFY
INT_STAT_LIST6_CO
MPLETE
INT_STAT_LIST5_NO
TIFY
INT_STAT_LIST5_CO
MPLETE
INT_STAT_LIST4_NO
TIFY
INT_STAT_LIST4_CO
MPLETE
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
7
6
5
4
3
2
1
0
INT_STAT_LIST3_NO
TIFY
INT_STAT_LIST3_CO
MPLETE
INT_STAT_LIST2_NO
TIFY
INT_STAT_LIST2_CO
MPLETE
INT_STAT_LIST1_NO
TIFY
INT_STAT_LIST1_CO
MPLETE
INT_STAT_LIST0_NO
TIFY
INT_STAT_LIST0_CO
MPLETE
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-283. VPDMA_int2_list0_int_stat Register Field Descriptions
Bit
Field
Type
Reset
Description
31
INT_STAT_CONTROL_D
ESCRIPTOR_INT15
W
0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 15. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
30
INT_STAT_CONTROL_D
ESCRIPTOR_INT14
W
0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 14. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
29
INT_STAT_CONTROL_D
ESCRIPTOR_INT13
W
0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 13. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
28
INT_STAT_CONTROL_D
ESCRIPTOR_INT12
W
0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 12. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
27
INT_STAT_CONTROL_D
ESCRIPTOR_INT11
W
0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 11. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
26
INT_STAT_CONTROL_D
ESCRIPTOR_INT10
W
0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 10. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
25
INT_STAT_CONTROL_D
ESCRIPTOR_INT9
W
0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 9. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
24
INT_STAT_CONTROL_D
ESCRIPTOR_INT8
W
0h
A Send Interrupt Control Descriptor has been received by the list
manager with a source value of 8. This event will cause a one to be
set in this register until cleared by software. Write a 1 to this field to
clear the value.
