Internal Modules
255
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
Table 1-105. VPDMA Channels (continued)
Channel
Description
Channel Number
Data Type
Client
grpx3_clut
Graphics 2 Color Lookup
Table Load from Memory
37
OTHER ()
grpx3_clut_clt (2)
vip1_mult_porta_src0
Video Input 1 Port A
Channel 0
38
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src1
Video Input 1 Port A
Channel 1
39
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src2
Video Input 1 Port A
Channel 2
40
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src3
Video Input 1 Port A
Channel 3
41
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src4
Video Input 1 Port A
Channel 4
42
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src5
Video Input 1 Port A
Channel 5
43
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src6
Video Input 1 Port A
Channel 6
44
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src7
Video Input 1 Port A
Channel 7
45
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src8
Video Input 1 Port A
Channel 8
46
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src9
Video Input 1 Port A
Channel 9
47
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src10
Video Input 1 Port A
Channel 10
48
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src11
Video Input 1 Port A
Channel 11
49
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src12
Video Input 1 Port A
Channel 12
50
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src13
Video Input 1 Port A
Channel 13
51
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src14
Video Input 1 Port A
Channel 14
52
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_porta_src15
Video Input 1 Port A
Channel 15
53
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_y (2)
vip1_mult_portb_src0
Video Input 1 Port B
Channel 0
54
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src1
Video Input 1 Port B
Channel 1
55
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src2
Video Input 1 Port B
Channel 2
56
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src3
Video Input 1 Port B
Channel 3
57
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src4
Video Input 1 Port B
Channel 4
58
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src5
Video Input 1 Port B
Channel 5
59
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src6
Video Input 1 Port B
Channel 6
60
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src7
Video Input 1 Port B
Channel 7
61
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src8
Video Input 1 Port B
Channel 8
62
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src9
Video Input 1 Port B
Channel 9
63
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)
vip1_mult_portb_src10
Video Input 1 Port B
Channel 10
64
YUV (0x7, 0x17, 0x27,
0x37)
vip1_lo_uv (1)