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DAxS
CVBS
Y
C
DAIV
DADC
DAUPS
2x
Oversampling
DAOUT
DALVL
Internal Modules
127
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.2.6.2.14.4 DAC Power Down
DAC power down is managed by the DA0E-DA1E registers. The corresponding DAC should be enabled
by setting these registers to 1. Otherwise, DAC should be in power down state. Both DACs can be power
down independently. By default, these registers are set to 0 to disable all DACs.
1.2.6.2.14.5 DAC DC Output Mode
A test mode to output the specified DC level on the DAC output pins is available. Setting DADC register to
1 switches DAC output from normal video signal to DALVL register. In this mode, both DACs have same
DC output of DALVL D/A converted value.
Figure 1-71. DAC I/F Logic