Texas Instruments DM38x DaVinci, User Manual

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Registers
871 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.53 SD_VENC_dactst Register (offset = 15Ch) [reset = 0h]
SD_VENC_dactst is shown in Figure 1-548 and described in Table 1-464 .
DAC Test Mode
Figure 1-548. SD_VENC_dactst Register
31 30 29 28 27 26 25 24
Reserved
R-0h
23 22 21 20 19 18 17 16
Reserved DAIV DADC
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
Reserved DALVL
R-0h R/W-0h
7 6 5 4 3 2 1 0
DALVL
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-464. SD_VENC_dactst Register Field Descriptions
Bit Field Type Reset Description
31-18 Reserved R 0h
17 DAIV R/W 0h
DAC output invert mode. Setting 1 inverts the DAC output code. 0:
Non-Inverse 1: Inverse
16 DADC R/W 0h
DAC DC output mode. Setting 1 converts the value written in the
DALVL register to DAC and directly outputs from DAOUT. 0: Normal
1: DC output mode
15-12 Reserved R 0h
11-0 DALVL R/W 0h
DAC DC level control