Texas Instruments DM38x DaVinci, User Manual

Page: 586 / 956

Registers
www.ti.com
586 SPRUHI7A – December 2012 – Revised June 2016
Submit Documentation Feedback
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.52 VPDMA_int1_list0_int_mask Register (offset = DCh) [reset = 0h]
VPDMA_int1_list0_int_mask is shown in Figure 1-352 and described in Table 1-264 .
Figure 1-352. VPDMA_int1_list0_int_mask Register
31 30 29 28 27 26 25 24
INT_MASK_CONTRO
L_DESCRIPTOR_INT
15
INT_MASK_CONTRO
L_DESCRIPTOR_INT
14
INT_MASK_CONTRO
L_DESCRIPTOR_INT
13
INT_MASK_CONTRO
L_DESCRIPTOR_INT
12
INT_MASK_CONTRO
L_DESCRIPTOR_INT
11
INT_MASK_CONTRO
L_DESCRIPTOR_INT
10
INT_MASK_CONTRO
L_DESCRIPTOR_INT
9
INT_MASK_CONTRO
L_DESCRIPTOR_INT
8
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
23 22 21 20 19 18 17 16
INT_MASK_CONTRO
L_DESCRIPTOR_INT
7
INT_MASK_CONTRO
L_DESCRIPTOR_INT
6
INT_MASK_CONTRO
L_DESCRIPTOR_INT
5
INT_MASK_CONTRO
L_DESCRIPTOR_INT
4
INT_MASK_CONTRO
L_DESCRIPTOR_INT
3
INT_MASK_CONTRO
L_DESCRIPTOR_INT
2
INT_MASK_CONTRO
L_DESCRIPTOR_INT
1
INT_MASK_CONTRO
L_DESCRIPTOR_INT
0
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
INT_MASK_LIST7_N
OTIFY
INT_MASK_LIST7_C
OMPLETE
INT_MASK_LIST6_N
OTIFY
INT_MASK_LIST6_C
OMPLETE
INT_MASK_LIST5_N
OTIFY
INT_MASK_LIST5_C
OMPLETE
INT_MASK_LIST4_N
OTIFY
INT_MASK_LIST4_C
OMPLETE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
INT_MASK_LIST3_N
OTIFY
INT_MASK_LIST3_C
OMPLETE
INT_MASK_LIST2_N
OTIFY
INT_MASK_LIST2_C
OMPLETE
INT_MASK_LIST1_N
OTIFY
INT_MASK_LIST1_C
OMPLETE
INT_MASK_LIST0_N
OTIFY
INT_MASK_LIST0_C
OMPLETE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-264. VPDMA_int1_list0_int_mask Register Field Descriptions
Bit Field Type Reset Description
31 INT_MASK_CONTROL_D
ESCRIPTOR_INT15 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
30 INT_MASK_CONTROL_D
ESCRIPTOR_INT14 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
29 INT_MASK_CONTROL_D
ESCRIPTOR_INT13 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
28 INT_MASK_CONTROL_D
ESCRIPTOR_INT12 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
27 INT_MASK_CONTROL_D
ESCRIPTOR_INT11 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
26 INT_MASK_CONTROL_D
ESCRIPTOR_INT10 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
25 INT_MASK_CONTROL_D
ESCRIPTOR_INT9 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
24 INT_MASK_CONTROL_D
ESCRIPTOR_INT8 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
23 INT_MASK_CONTROL_D
ESCRIPTOR_INT7 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.
22 INT_MASK_CONTROL_D
ESCRIPTOR_INT6 R/W 0h
The interrupt for should generate an interrupt on interrupt
vpdma_int1. Write a 1 for the interrupt event to trigger the interrupt
signal.