Texas Instruments DM38x DaVinci, User Manual

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Registers
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842 SPRUHI7A – December 2012 – Revised June 2016
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High-Definition Video Processing Subsystem (HDVPSS)
1.3.12.24 SD_VENC_cvbs0 Register (offset = 9Ch) [reset = 034400BCh]
SD_VENC_cvbs0 is shown in Figure 1-519 and described in Table 1-435 .
CVBS Control 0
Figure 1-519. SD_VENC_cvbs0 Register
31 30 29 28 27 26 25 24
Reserved CSLVL
R-0h R/W-344h
23 22 21 20 19 18 17 16
CSLVL
R/W-344h
15 14 13 12 11 10 9 8
Reserved CTLVL
R-0h R/W-BCh
7 6 5 4 3 2 1 0
CTLVL
R/W-BCh
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 1-435. SD_VENC_cvbs0 Register Field Descriptions
Bit Field Type Reset Description
31-28 Reserved R 0h
27-16 CSLVL R/W 344h
CVBS sync amplitude.
15-12 Reserved R 0h
11-0 CTLVL R/W BCh
CVBS sync-tip amplitude.