Registers
696
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.89 VPDMA_int3_client1_int_stat Register (offset = 170h) [reset = 0h]
VPDMA_int3_client1_int_stat is shown in
and described in
Figure 1-389. VPDMA_int3_client1_int_stat Register
31
30
29
28
27
26
25
24
Reserved
INT_STAT_VIP2_AN
C_B
INT_STAT_VIP2_AN
C_A
INT_STAT_VIP1_AN
C_B
INT_STAT_VIP1_AN
C_A
INT_STAT_TRANS2_
LUMA
INT_STAT_TRANS2_
CHROMA
R-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
23
22
21
20
19
18
17
16
INT_STAT_TRANS1_
LUMA
INT_STAT_TRANS1_
CHROMA
INT_STAT_HDMI_WR
BK_OUT
INT_STAT_VPI_CTL
INT_STAT_VBI_SDV
ENC
Reserved
INT_STAT_NF_420_
UV_OUT
INT_STAT_NF_420_Y
_OUT
W-0h
W-0h
W-0h
W-0h
W-0h
R-0h
W-0h
W-0h
15
14
13
12
11
10
9
8
INT_STAT_NF_420_
UV_IN
INT_STAT_NF_420_Y
_IN
INT_STAT_NF_422_I
N
INT_STAT_GRPX3_S
T
INT_STAT_GRPX2_S
T
INT_STAT_GRPX1_S
T
INT_STAT_VIP2_UP_
UV
INT_STAT_VIP2_UP_
Y
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
7
6
5
4
3
2
1
0
INT_STAT_VIP2_LO_
UV
INT_STAT_VIP2_LO_
Y
INT_STAT_VIP1_UP_
UV
INT_STAT_VIP1_UP_
Y
INT_STAT_VIP1_LO_
UV
INT_STAT_VIP1_LO_
Y
INT_STAT_GRPX3_D
ATA
INT_STAT_GRPX2_D
ATA
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-301. VPDMA_int3_client1_int_stat Register Field Descriptions
Bit
Field
Type
Reset
Description
31-30
Reserved
R
0h
29
INT_STAT_VIP2_ANC_B
W
0h
The client interface vip2_anc_b has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
28
INT_STAT_VIP2_ANC_A
W
0h
The client interface vip2_anc_a has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
27
INT_STAT_VIP1_ANC_B
W
0h
The client interface vip1_anc_b has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
26
INT_STAT_VIP1_ANC_A
W
0h
The client interface vip1_anc_a has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having received the End of Frame signal from the
transmitting module. This event will cause a one to be set in this
register until cleared by software. Write a 1 to this field to clear the
value.
25
INT_STAT_TRANS2_LU
MA
W
0h
The client interface trans2_luma has reached its current configured
interrupt event as specified by the last received control descriptor for
this client. If no control descriptor has been configured this will
default to having sent the End of Frame signal to the receiving
module. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
