Registers
682
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.3.8.83 VPDMA_int3_channel5_int_stat Register (offset = 158h) [reset = 0h]
VPDMA_int3_channel5_int_stat is shown in
and described in
Figure 1-383. VPDMA_int3_channel5_int_stat Register
31
30
29
28
27
26
25
24
INT_STAT_TRANSC
ODE2_CHROMA
INT_STAT_TRANSC
ODE2_LUMA
INT_STAT_TRANSC
ODE1_CHROMA
INT_STAT_TRANSC
ODE1_LUMA
INT_STAT_AUX_IN
INT_STAT_PIP_FRA
ME
INT_STAT_POST_CO
MP_WR
INT_STAT_VBI_SD_V
ENC
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
23
22
21
20
19
18
17
16
Reserved
INT_STAT_NF_LAST
_CHROMA
INT_STAT_NF_LAST
_LUMA
INT_STAT_NF_WRIT
E_CHROMA
INT_STAT_NF_WRIT
E_LUMA
INT_STAT_NF_READ INT_STAT_VIP2_PO
RTB_RGB
INT_STAT_VIP2_PO
RTA_RGB
R-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
15
14
13
12
11
10
9
8
INT_STAT_VIP2_PO
RTB_CHROMA
INT_STAT_VIP2_PO
RTB_LUMA
INT_STAT_VIP2_PO
RTA_CHROMA
INT_STAT_VIP2_PO
RTA_LUMA
INT_STAT_VIP2_MU
LT_ANCB_SRC15
INT_STAT_VIP2_MU
LT_ANCB_SRC14
INT_STAT_VIP2_MU
LT_ANCB_SRC13
INT_STAT_VIP2_MU
LT_ANCB_SRC12
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
7
6
5
4
3
2
1
0
INT_STAT_VIP2_MU
LT_ANCB_SRC11
INT_STAT_VIP2_MU
LT_ANCB_SRC10
INT_STAT_VIP2_MU
LT_ANCB_SRC9
INT_STAT_VIP2_MU
LT_ANCB_SRC8
INT_STAT_VIP2_MU
LT_ANCB_SRC7
INT_STAT_VIP2_MU
LT_ANCB_SRC6
INT_STAT_VIP2_MU
LT_ANCB_SRC5
INT_STAT_VIP2_MU
LT_ANCB_SRC4
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit;
-n
= value after reset
Table 1-295. VPDMA_int3_channel5_int_stat Register Field Descriptions
Bit
Field
Type
Reset
Description
31
INT_STAT_TRANSCODE
2_CHROMA
W
0h
The last read DMA transaction has occurred for channel
transcode2_chroma and the channel is free to be updated for the
next transfer. This will fire before the destination has received the
data as it will have just been stored in the internal buffer. The client
trans2_chroma will now accept a new descriptor from the List
Manager. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
30
INT_STAT_TRANSCODE
2_LUMA
W
0h
The last read DMA transaction has occurred for channel
transcode2_luma and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client
trans2_luma will now accept a new descriptor from the List Manager.
This event will cause a one to be set in this register until cleared by
software. Write a 1 to this field to clear the value.
29
INT_STAT_TRANSCODE
1_CHROMA
W
0h
The last read DMA transaction has occurred for channel
transcode1_chroma and the channel is free to be updated for the
next transfer. This will fire before the destination has received the
data as it will have just been stored in the internal buffer. The client
trans1_chroma will now accept a new descriptor from the List
Manager. This event will cause a one to be set in this register until
cleared by software. Write a 1 to this field to clear the value.
28
INT_STAT_TRANSCODE
1_LUMA
W
0h
The last read DMA transaction has occurred for channel
transcode1_luma and the channel is free to be updated for the next
transfer. This will fire before the destination has received the data as
it will have just been stored in the internal buffer. The client
trans1_luma will now accept a new descriptor from the List Manager.
This event will cause a one to be set in this register until cleared by
software. Write a 1 to this field to clear the value.
27
INT_STAT_AUX_IN
W
0h
The last read DMA transaction has occurred for channel aux_in and
the channel is free to be updated for the next transfer. This will fire
before the destination has received the data as it will have just been
stored in the internal buffer. The client comp_wrbk will now accept a
new descriptor from the List Manager. This event will cause a one to
be set in this register until cleared by software. Write a 1 to this field
to clear the value.
