Internal Modules
178
SPRUHI7A – December 2012 – Revised June 2016
Copyright © 2012–2016, Texas Instruments Incorporated
High-Definition Video Processing Subsystem (HDVPSS)
1.2.8.2.19 VIP Overflow Detection and Recovery
It is possible that an overflow can occur in the VIP_PARSER. Overflow detection is determined by reading
the VIP_PARSER_fiq_status register and checking for bits 8, 7, 5, 4, 3 and 2. If video is being captured,
and any of these bits are set, it indicates that not all of the incoming video data was sent to DDR. VIP
Overflow can be caused by one of the following:
1. External pixel clock is faster than processing clock
2. DDR bandwidth is temporarily over-consumed
3. VIP scaler is being used inline with external video input, and is upscaling.
•
VIP scaler in this use case can only be used for downscaling
4. VIP scaler is being used inline with external video input, but has not been configured with scaler
coefficients
•
VIP scaler will not accept video input if it is not first configured with scaler coefficients. This will
cause overflow
5. VIP scaler is being used inline, but has not been enabled
6. External cables are connected or disconnected while the system is running, resulting in corrupted
video streams going into the VIP
7. Bad external video cable, which causes corrupted video streams going into the VIP
Items 6 and 7 are typically seen as noise events, where it is likely that multiple horizontal syncs per line
and/or multiple vertical syncs per frame will be observed. These result in high peak throughput
requirements, leading to DDR bandwidth being temporarily over-consumed, and thus VIP overflow.
The high level recovery method for VIP Overflow on port a is outlined below. Port b is similar :
1. Set yuv_srcnum_stop_immediately = 0xFFFF_FFFF
2. Set anc_srcnum_stop_immediately = 0xFFFF_FFFF
3. Set ENABLE = 0
4. Set CLR_ASYNC_FIFO_RD and CLR_ASYNC_FIFO_WR to 1
5. Set SW_RESET to 1
6. Reset Other VIP modules
•
For each module used downstream of VIP_PARSER, write 1 to the bit location of the clkc_rst
register which is connected to VIP_PARSER (will be bits 20-23 and 25-28)
7. Abort VPDMA channels
•
Write to list attribute to stop list 0
•
Write to list address register location of abort list
•
Write to list attribute register list 0 and size of abort list
8. Set SW_RESET to 0
9. Un-reset Other VIP modules
•
For each module used downstream of VIP_PARSER, write 0 to the bit location of the clkc_rst
register which is connected to VIP_PARSER (will be bits 20-23 and 25
10. (Delay)
11. SC coeff downloaded (if VIP_SCALER is being used)
12. (Delay)
13. Set yuv_srcnum_stop_immediately = 0x0000_0000
14. Set anc_srcnum_stop_immediately = 0x0000_0000
15. Set ENABLE = 1
16. Set CLR_ASYNC_FIFO_RD and CLR_ASYNC_FIFO_WR to 0
